test.vhd

数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位

library ieee;
use ieee.std_logic_1164.all;

entity test is end;

architecture behav of test is
   component frequnce
      port(FSIN : in std_logic; 
            clk : in std_logic;
        sel_led : out std_logic_vector(2 downto 0);
       data_out : out std_logic_vector(6 downto 0));
   end component;
   signal fin,clkin : std_logic;
   signal dig : std_logic_vector(2 downto 0);
   signal leddata : std_logic_vector(6 downto 0);
begin
   uut : frequnce port map (fsin=>fin, clk=>clkin, sel_led=>dig, data_out=>leddata);
   process
   begin
      clkin <= '1';
      wait for 50 ns;
      clkin <= '0';
      wait for 50 ns;
   end process;
   process
   begin
      fin <= '1';
      wait for 40 ns;
      fin <= '0';
      wait for 40 ns;
   end process;
end;