frequnce.vhd

数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity frequnce is
port(FSIN: in std_logic; 
     clk: in std_logic;
     sel_led: out std_logic_vector(2 downto 0);
     data_out: out std_logic_vector(6 downto 0));
end frequnce;


architecture behav of frequnce is

   type freq_value is array (1 to 8) of std_logic_vector(3 downto 0);

   component  divfre
      generic(rate: integer range 0 to 255 :=10);
      port(fin:in std_logic;
          fout:out std_logic);
   end component;
   
   component  cnt10
      port(clk:in std_logic;
           clr:in std_logic;
            ci:in std_logic;    						  --  carry in
            cq:out std_logic_vector(3 downto 0);  --  4wei ji 'shu jie guo
            co: out std_logic);    						  --  carry out
   end component;
   
   signal f5hz,f1khz,f100khz: std_logic;
   signal carry: std_logic_vector(0 to 8);
   signal test_en: std_logic;
   signal clear: std_logic;
   signal load: std_logic;
   signal cnt_value,latched_value : freq_value;
   signal sel : std_logic_vector(2 downto 0) := "000";
   signal data : std_logic_vector(3 downto 0);
      
begin

   fdiv1 : divfre generic map (rate=>100) port map (fin=>clk,fout=>f100khz); 
   fdiv2 : divfre generic map (rate=>100) port map (fin=>f100khz,fout=>f1khz);
   fdiv3: divfre generic map (rate=>200) port map (fin=>f1khz,fout=>f5hz); 
   
   process(f5hz)
      variable sta1 : std_logic_vector(2 downto 0):="000";
   begin
      if f5hz'event and f5hz='1' then
         sta1 := sta1 + 1;
      end if;
      if sta1 > "010" then test_en <= '1';else test_en <= '0'; end if;
      if sta1 = "000" then load <= '1';else load <= '0'; end if;
      if sta1 = "001" then clear <= '1';else clear <= '0'; end if;
   end process;
   
   carry(0)<=test_en;
   
   counter : for i in 1 to 8 generate
      cq : cnt10 port map (clk=>fsin,clr=>clear,ci=>carry(i-1),cq=>cnt_value(i),co=>carry(i));
   end generate;
   
   process(load,cnt_value)
   begin
      if load='1' then
         latched_value <= cnt_value;
      end if;
   end process;
   
   process(f1khz)
   begin
      if f1khz'event and f1khz='1' then
         sel <= sel + 1;
      end if;
   end process;
   
   process(sel,latched_value)
   begin
      case sel is
         when "000" => data <= latched_value(1);
         when "001" => data <= latched_value(2);
         when "010" => data <= latched_value(3);
         when "011" => data <= latched_value(4);
         when "100" => data <= latched_value(5);
         when "101" => data <= latched_value(6);
         when "110" => data <= latched_value(7);
         when "111" => data <= latched_value(8);
         when others => data <= "----";
      end case;
   end process;
   
   process(data)
   begin
      case data is
         when "0000" => data_out <= "1111110";
         when "0001" => data_out <= "0110000";
         when "0010" => data_out <= "1101101";
         when "0011" => data_out <= "1111001";
         when "0100" => data_out <= "0110011";
         when "0101" => data_out <= "1011011";
         when "0110" => data_out <= "1011111";
         when "0111" => data_out <= "1110000";
         when "1000" => data_out <= "1111111";
         when "1001" => data_out <= "1111011";
         when others => data_out <= "-------";
      end case;
   end process;  
   
   sel_led<=sel; 
   
end behav;