📄 receive.rpt
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bit_collect_1.CLKF = clock_pluse
bit_collect_1.PRLD = GND
clock_div_0 := /clock_div_6.FBK.LFBK * /clock_div_0.FBK.LFBK
+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK *
/clock_div_5.FBK.LFBK * /clock_div_0.FBK.LFBK
clock_div_0.CLKF = /clock ;FCLK/GCK
clock_div_0.PRLD = GND
clock_div_1 := /clock_div_6.FBK.LFBK * clock_div_0.FBK.LFBK *
/clock_div_1.FBK.LFBK
+ /clock_div_6.FBK.LFBK * /clock_div_0.FBK.LFBK *
clock_div_1.FBK.LFBK
+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK *
/clock_div_5.FBK.LFBK * clock_div_0.FBK.LFBK * /clock_div_1.FBK.LFBK
+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK *
/clock_div_5.FBK.LFBK * /clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK
clock_div_1.CLKF = /clock ;FCLK/GCK
clock_div_1.PRLD = GND
clock_div_2.T = clock_div_6.FBK.LFBK * clock_div_4.FBK.LFBK *
clock_div_2.FBK.LFBK
+ clock_div_6.FBK.LFBK * clock_div_5.FBK.LFBK *
clock_div_2.FBK.LFBK
+ /clock_div_6.FBK.LFBK * clock_div_0.FBK.LFBK *
clock_div_1.FBK.LFBK
+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK *
/clock_div_5.FBK.LFBK * clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK
;Imported pterms FB3_1
+ clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK *
clock_div_2.FBK.LFBK
clock_div_2.CLKF = /clock ;FCLK/GCK
clock_div_2.PRLD = GND
clock_div_3.T = clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK
+ /clock_div_6.FBK.LFBK * clock_div_0.FBK.LFBK *
clock_div_1.FBK.LFBK * clock_div_2.FBK.LFBK
+ /clock_div_4.FBK.LFBK * /clock_div_5.FBK.LFBK *
clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK * clock_div_2.FBK.LFBK
clock_div_3.CLKF = /clock ;FCLK/GCK
clock_div_3.PRLD = GND
clock_div_4.T = clock_div_6.FBK.LFBK * clock_div_4.FBK.LFBK
+ /clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK *
clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK * clock_div_2.FBK.LFBK
clock_div_4.CLKF = /clock ;FCLK/GCK
clock_div_4.PRLD = GND
clock_div_5.T = clock_div_6.FBK.LFBK * clock_div_5.FBK.LFBK
+ /clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK *
clock_div_4.FBK.LFBK * clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK *
clock_div_2.FBK.LFBK
clock_div_5.CLKF = /clock ;FCLK/GCK
clock_div_5.PRLD = GND
clock_div_6 := clock_div_6.FBK.LFBK * /clock_div_3.FBK.LFBK *
/clock_div_4.FBK.LFBK * /clock_div_5.FBK.LFBK
+ /clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK *
clock_div_4.FBK.LFBK * clock_div_5.FBK.LFBK * clock_div_0.FBK.LFBK *
clock_div_1.FBK.LFBK * clock_div_2.FBK.LFBK
clock_div_6.CLKF = /clock ;FCLK/GCK
clock_div_6.PRLD = GND
/clock_pluse := /clock_div_6.FBK.LFBK
+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK *
/clock_div_5.FBK.LFBK
clock_pluse.CLKF = /clock ;FCLK/GCK
clock_pluse.PRLD = GND
/count_reg_0.T = ;Imported pterms FB5_14
rxd * /rxd_start_reg.FBK.LFBK
+ /count_reg_0.FBK.LFBK * /rxd_start_reg.FBK.LFBK
+ count_reg_2 * count_reg_3 * /count_reg_0.FBK.LFBK *
count_reg_1.FBK.LFBK
count_reg_0.CLKF = clock_pluse
count_reg_0.PRLD = GND
count_reg_1.T = count_reg_0.FBK.LFBK * rxd_start_reg.FBK.LFBK
;Imported pterms FB5_13
+ /rxd * count_reg_1.FBK.LFBK *
/rxd_start_reg.FBK.LFBK
+ count_reg_2 * count_reg_3 * count_reg_1.FBK.LFBK *
rxd_start_reg.FBK.LFBK
count_reg_1.CLKF = clock_pluse
count_reg_1.PRLD = GND
count_reg_2.T = /rxd * /rxd_start_reg * count_reg_2.FBK.LFBK
+ rxd_start_reg * count_reg_0 * count_reg_1
+ rxd_start_reg * count_reg_1 *
count_reg_2.FBK.LFBK * count_reg_3.FBK.LFBK
count_reg_2.CLKF = clock_pluse.FBK.LFBK
count_reg_2.PRLD = GND
count_reg_3.T = /rxd * /rxd_start_reg * count_reg_3.FBK.LFBK
+ rxd_start_reg * count_reg_0 * count_reg_1 *
count_reg_2.FBK.LFBK
+ rxd_start_reg * count_reg_1 *
count_reg_2.FBK.LFBK * count_reg_3.FBK.LFBK
count_reg_3.CLKF = clock_pluse.FBK.LFBK
count_reg_3.PRLD = GND
/rxd_start_reg := /bit_cnt_0.FBK.LFBK * bit_cnt_2.FBK.LFBK *
bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK *
/bit_cnt_2.FBK.LFBK * bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK *
count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK
+ rxd * count_reg_2 * /count_reg_3 *
/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK *
count_reg_1.FBK.LFBK
+ rxd * count_reg_2 * /count_reg_3 *
/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK *
bit_collect_0.FBK.LFBK
;Imported pterms FB5_15
+ bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK *
bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
+ bit_cnt_1.FBK.LFBK * bit_cnt_3.FBK.LFBK *
/count_reg_0.FBK.LFBK * rxd_start_reg.FBK.LFBK
+ bit_cnt_1.FBK.LFBK * bit_cnt_3.FBK.LFBK *
/count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK
+ /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK *
bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
;Imported pterms FB5_17
+ rxd * /rxd_start_reg.FBK.LFBK
+ /count_reg_2 * bit_cnt_1.FBK.LFBK *
bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
+ count_reg_3 * bit_cnt_1.FBK.LFBK *
bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK *
/bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK *
count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK *
bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK
rxd_start_reg.CLKF = clock_pluse
rxd_start_reg.PRLD = GND
**************************** Device Pin Out ****************************
Device : XC95108-7-PC84
c
l
T T o G T T T T T T r T T T T T T V T T T
I I c N I I I I I I x I I I I I I C I I I
E E k D E E E E E E d E E E E E E C E E E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | TIE
TIE | 15 71 | TIE
GND | 16 70 | TIE
TIE | 17 69 | TIE
TIE | 18 68 | TIE
TIE | 19 67 | TIE
TIE | 20 66 | TIE
TIE | 21 XC95108-7-PC84 65 | TIE
VCC | 22 64 | VCC
TIE | 23 63 | TIE
TIE | 24 62 | TIE
TIE | 25 61 | TIE
TIE | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | TIE
TMS | 29 57 | TIE
TCK | 30 56 | TIE
sbuf<7> | 31 55 | TIE
sbuf<6> | 32 54 | TIE
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
s s s s s V s T T G T T T T T T G T T T T
b b b b b C b I I N I I I I I I N I I I I
u u u u u C u E E D E E E E E E D E E E E
f f f f f f
< < < < < <
5 4 3 2 1 0
> > > > > >
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC95108-7-PC84
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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