📄 send.bld

📁 结合XILINXCPLD所做的模拟RS232通信verilog源程序

💻 BLD

字号:

Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc send.ucf -p XC9500 send.ngc send.ngd Reading NGO file "C:/WINDOWS/Desktop/send/send.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_10"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_10 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_4"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_4 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_5"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_5 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_6"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_6 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_7"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_7 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_8"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_8 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_9"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_9 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Annotating constraints to design from file "send.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "send.ngd" ...Writing NGDBUILD log file "send.bld"...

💿 文件大小 120 K

👤 上传用户 c_word

📂 所属分类 VHDL/FPGA/Verilog

🏷️ 相关标签

#XILINXCPLD #verilog #232 #RS

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