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来自「用verilog编写的网卡芯片rtl级。前仿后仿都通过了」· 代码 · 共 10 行

# Reading C:/Program Files/Modeltech_5.6/win32/../tcl/vsim/pref.tcl 
# vsim {C:\DOCUME~1\liu\桌面\OURPRO~1\网关项?\ethernet\rtl\verilog\ETH_RX~4.V} 
# ** Error: (vsim-19) Failed to access library 'work' at "work".
# No such file or directory.
# Error loading design
# Load canceled
# Load canceled
file mkdir C:/verilong_trial/eth_model
# Loading project eth_modell