part_mul.vhd

自已写的一个16X16的乘法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity part_mul is 
  port(ina : in std_logic_vector(15 downto 0);
       inb : in std_logic_vector(1 downto 0);
       mout : out std_logic_vector(17 downto 0));
end part_mul;

architecture arc of part_mul is
begin
  process(ina , inb)
  begin
    case inb is
    when "00" => mout <= "000000000000000000";
    when "01" => mout(15 downto 0) <= ina(15 downto 0);
                 mout(17 downto 16) <= "00";
    when "10" => mout(0) <= '0';
                 mout(16 downto 1) <= ina(15 downto 0);
                 mout(17) <= '0';
    when others => mout <= ("00" & ina) + ('0' & ina & '0');
    end case;
  end process;
end arc;