mul_16.vhd

自已写的一个16X16的乘法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mul_16 is
  port(dina : in std_logic_vector(15 downto 0);
       dinb : in std_logic_vector(15 downto 0);
       mout : out std_logic_vector(31 downto 0));
end mul_16;

architecture arc of mul_16 is
signal a1 : std_logic_vector(17 downto 0);
signal a2 : std_logic_vector(17 downto 0);
signal a3 : std_logic_vector(17 downto 0);
signal a4 : std_logic_vector(17 downto 0);
signal a5 : std_logic_vector(17 downto 0);
signal a6 : std_logic_vector(17 downto 0);
signal a7 : std_logic_vector(17 downto 0);
signal a8 : std_logic_vector(17 downto 0);
signal b1 : std_logic_vector(19 downto 0);
signal b2 : std_logic_vector(19 downto 0);
signal b3 : std_logic_vector(19 downto 0);
signal b4 : std_logic_vector(19 downto 0);
signal c1 : std_logic_vector(23 downto 0);
signal c2 : std_logic_vector(23 downto 0);

component part_mul
  port(ina : in std_logic_vector(15 downto 0);
       inb : in std_logic_vector(1 downto 0);
       mout : out std_logic_vector(17 downto 0));
end component;

component adder_2 
  port(dataa : in std_logic_vector(17 downto 0);
       datab : in std_logic_vector(17 downto 0);
       sout : out std_logic_vector(19 downto 0));
end component;

component adder_4
  port(dataa : in std_logic_vector(19 downto 0);
       datab : in std_logic_vector(19 downto 0);
       sout : out std_logic_vector(23 downto 0));
end component;

component adder_8
  port(dataa : in std_logic_vector(23 downto 0);
       datab : in std_logic_vector(23 downto 0);
       sout : out std_logic_vector(31 downto 0));
end component;
begin
u1:part_mul port map (dina , dinb(1 downto 0) , a1);
u2:part_mul port map (dina , dinb(3 downto 2) , a2);
u3:part_mul port map (dina , dinb(5 downto 4) , a3);
u4:part_mul port map (dina , dinb(7 downto 6) , a4);
u5:part_mul port map (dina , dinb(9 downto 8) , a5);
u6:part_mul port map (dina , dinb(11 downto 10) , a6);
u7:part_mul port map (dina , dinb(13 downto 12) , a7);
u8:part_mul port map (dina , dinb(15 downto 14) , a8);
u9:adder_2 port map (a1 , a2 , b1);
u10:adder_2 port map (a3 , a4 , b2);
u11:adder_2 port map (a5 , a6 , b3);
u12:adder_2 port map (a7 , a8 , b4);
u13:adder_4 port map (b1 , b2 , c1);
u14:adder_4 port map (b3 , b4 , c2);
u15:adder_8 port map (c1 , c2 , mout);
end arc;