mega.elb

這是用verilog寫的一個簡單的處理器

(_unit VERILOG 1.152.1.136 (SAP_1_tb 0 9 (SAP_1_tb 0 9 ))
	(_version v27)
	(_time 1117625255825 2005.06.01 19:27:35)
	(_source (\.\\src\\TestBench\\SAP_1_TB.v\))
	(_use (std(standard))(vl(verilog_logic)))
	(_entity
		(_time 1117625255825)
		(_use )
	)
	(_timescale 1ns 100ps)
	(_object
		(_signal (_internal asy_rst ~reg 0 13 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal clk ~reg 0 14 (_architecture (_uni ))) (_reg ) (_simple))
		(_type (_internal ~[7:0]wire~ 0 15 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal Oreg ~[7:0]wire~ 0 15 (_architecture (_uni ))) (_net  ) (_simple))
		(_signal (_internal go ~reg 0 16 (_architecture (_uni ))) (_reg ) (_simple))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (std standard real)))
		(_type (_external ~realtime (std standard real)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INITIAL#27_0 (_architecture 0 0 27 (_process (_target(0)(3)))))
			(#ALWAYS#38_1 (_architecture 1 0 38 (_process (_target(1)))))
		)
	)
	(_scope
	)
	(_instantiation UUT 0 25 (_entity . SAP_1)
		(_port
			((asy_rst) (asy_rst))
			((clk) (clk))
			((Oreg) (Oreg))
			((go) (go))
		)
	)
	(_model . SAP_1_tb 3 -1)

)