sap_1_tb.v

這是用verilog寫的一個簡單的處理器

//* This automatically generated file is a part of Verilog testbench.
//*   This file was generated by Active-HDL 4.1 (TB_verilog v.1.1).
//*   Copyright (C) ALDEC Inc.
//* This Verilog file contains the main Test Bench module
//* and is a part of Verilog Testbench for module "SAP_1"
//* This file was generated on: Wed Jun  1 17:54:05 2005

`timescale 1ns / 100ps
module SAP_1_tb;
	
	
	//Internal signals declarations:
	reg asy_rst;
	reg clk;
	wire [7:0]Oreg;
	reg go;
	
	
	
	// Unit Under Test port map
	SAP_1 UUT (
		.asy_rst(asy_rst),
		.clk(clk),
		.Oreg(Oreg),
		.go(go));
	
	initial
		begin
			asy_rst=1;
			go=0 ;
			#1000
			asy_rst=0;
			#100
			go=1;
			#100
			go=0;
		end
	always
		begin
			#20	clk=0;
			#20	clk=1;
		end
	
endmodule