📄 traffic_light.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity traffic_light is
port(x,y,clk: in std_logic;
z:out std_logic);
end traffic_light;
architecture arc of traffic_light is
type state_type is(a,b,c,d);
signal present_state,next_state:state_type;
signal comb: std_logic_vector(1 downto 0);
begin
nextstate_logic:
process(present_state,x,y)
begin
comb<=x&y;
case present_state is
when a => if(comb="00")then
next_state<=a;
elsif(comb="01" or comb="10") then
next_state<=b;
end if;
when b => if(comb="00")then
next_state<=c;
elsif(comb="01" or comb="10") then
next_state<=b;
end if;
when c => if(comb="00")then
next_state<=c;
elsif(comb="01" or comb="10") then
next_state<=d;
end if;
when d => if(comb="00")then
next_state<=a;
elsif(comb="01" or comb="10") then
next_state<=d;
end if;
end case;
end process;
state_register:
process(clk)
begin
if(clk'event and clk='1')then
present_state<=next_state;
end if;
end process;
output_logic:
process(present_state)
begin
case present_state is
when a=> z<='0';
when others => z<='1';
end case;
end process;
end arc;
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