vz_ver4.bld

该工程文件实现ARM系统中CPLD的逻辑工作

Release 3.1i - ngdbuild D.19
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -p xc9536xl-10-vq44 -uc vz_ver4.ucf -dd ..
d:\cpld_p~1\vz_ver4\vz_ver4.edn vz_ver4.ngd 

Launcher: Executing edif2ngd "d:\cpld_p~1\vz_ver4\vz_ver4.edn"
"D:\CPLD_project\vz_ver4\xproj\ver1\vz_ver4.ngo"
Release 3.1i - edif2ngd D.19
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.
Writing the design to "D:/CPLD_project/vz_ver4/xproj/ver1/vz_ver4.ngo"...
Reading NGO file "D:/CPLD_project/vz_ver4/xproj/ver1/vz_ver4.ngo" ...
Reading component libraries for design expansion...
Running LogiBLOX expansion on symbol "L1"...
WARNING:LBEngine:353 - Module lfsrnor : All styles for SIMPLE_GATES are
   implemented identically  for the XC9500 family.WARNING:LBEngine:353 - Module lfsrnor : All styles for SIMPLE_GATES are
   implemented identically  for the XC9500 family.Launcher: "DE.ngo" is up to date.
Loading design module "D:\CPLD_project\vz_ver4\xproj\ver1\DE.ngo"...

Annotating constraints to design from file "vz_ver4.ucf" ...

Checking timing specifications ...

Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "vz_ver4.ngd" ...

Writing NGDBUILD log file "vz_ver4.bld"...