📄 vz_ver4.tim
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Performance Summary Report
--------------------------
Design: vz_ver4
Device: XC9536XL-10-VQ44
Speed File: Version 1.0
Program: Timing Report Generator: version D.19
Date: Mon Dec 09 16:54:38 2002
Performance Summary:
Pad to Pad (tPD) : 10.0ns (1 macrocell levels)
Pad 'A22' to Pad 'HPICE'
Clock net 'CLK' path delays:
Clock Pad to Output Pad (tCO) : 10.2ns (1 macrocell levels)
Clock Pad 'CLK' to Output Pad 'SYNC' (Pterm Clock)
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
Clock to Q, net 'L1/TERM_CNT2.Q' to TFF Setup(D) at 'L1/lfsr_counter2/Q_OUT7.D'(Pterm Clock)
Target FF drives output net 'L1/lfsr_counter2/Q_OUT7'
Minimum Clock Period: 14.0ns
Maximum Internal Clock Speed: 71.4Mhz
(Limited by Clock Pulse Width)
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A A D E R
\ 2 2 2 I X S
\ 0 1 2 S T T
\ P C I
\ L E N
\ A
\ Y
To \------------------------------------
DON 10.0
HPICE 10.0 10.0 10.0 10.0
NICCE 10.0 10.0 10.0 10.0
RST_VZ 10.0
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From C
\ L
\ K
\
\
\
\
To \------
SYNC 10.2
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK)
\ From L L L L L L L L L
\ 1 1 1 1 1 1 1 1 1
\ / / / / / / / / /
\ T T l l l l l l l
\ E E f f f f f f f
\ R R s s s s s s s
\ M M r r r r r r r
\ _ _ _ _ _ _ _ _ _
\ C C c c c c c c c
\ N N o o o o o o o
\ T T u u u u u u u
\ 1 2 n n n n n n n
\ . . t t t t t t t
\ Q Q e e e e e e e
\ r r r r r r r
\ 1 1 1 1 1 2 2
\ / / / / / / /
\ Q Q Q Q Q Q Q
\ _ _ _ _ _ _ _
\ O O O O O O O
\ U U U U U U U
\ T T T T T T T
\ 0 1 2 3 4 0 1
\ . . . . . . .
\ Q Q Q Q Q Q Q
\
To \------------------------------------------------------
L1/TERM_CNT1.CE
L1/TERM_CNT1.D 10.0 10.0 10.0 10.0 10.0 10.0
L1/TERM_CNT2.CE
L1/TERM_CNT2.D 10.0 10.0 10.0
L1/lfsr_counter1/Q_OUT0.CE
L1/lfsr_counter1/Q_OUT0.D 10.0 10.0
L1/lfsr_counter1/Q_OUT1.CE
L1/lfsr_counter1/Q_OUT1.D 10.0 10.0
L1/lfsr_counter1/Q_OUT2.CE
L1/lfsr_counter1/Q_OUT2.D 10.0 10.0
L1/lfsr_counter1/Q_OUT3.CE
L1/lfsr_counter1/Q_OUT3.D 10.0 10.0
L1/lfsr_counter1/Q_OUT4.CE
L1/lfsr_counter1/Q_OUT4.D 10.0 10.0 10.0
L1/lfsr_counter2/Q_OUT0.CE
L1/lfsr_counter2/Q_OUT0.D 10.0 10.0
L1/lfsr_counter2/Q_OUT1.CE
L1/lfsr_counter2/Q_OUT1.D 10.0
L1/lfsr_counter2/Q_OUT2.CE
L1/lfsr_counter2/Q_OUT2.D 10.0
L1/lfsr_counter2/Q_OUT3.CE
L1/lfsr_counter2/Q_OUT3.D 10.0
L1/lfsr_counter2/Q_OUT4.CE
L1/lfsr_counter2/Q_OUT4.D 10.0
L1/lfsr_counter2/Q_OUT5.CE
L1/lfsr_counter2/Q_OUT5.D 10.0
L1/lfsr_counter2/Q_OUT6.CE
L1/lfsr_counter2/Q_OUT6.D 10.0
L1/lfsr_counter2/Q_OUT7.CE
L1/lfsr_counter2/Q_OUT7.D 11.0 11.0 11.0
SYNC.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK)
\ From L L L L L L S
\ 1 1 1 1 1 1 Y
\ / / / / / / N
\ l l l l l l C
\ f f f f f f .
\ s s s s s s Q
\ r r r r r r
\ _ _ _ _ _ _
\ c c c c c c
\ o o o o o o
\ u u u u u u
\ n n n n n n
\ t t t t t t
\ e e e e e e
\ r r r r r r
\ 2 2 2 2 2 2
\ / / / / / /
\ Q Q Q Q Q Q
\ _ _ _ _ _ _
\ O O O O O O
\ U U U U U U
\ T T T T T T
\ 2 3 4 5 6 7
\ . . . . . .
\ Q Q Q Q Q Q
\
To \------------------------------------------
L1/TERM_CNT1.CE
L1/TERM_CNT1.D
L1/TERM_CNT2.CE
L1/TERM_CNT2.D 10.0 10.0 10.0 10.0 10.0 10.0
L1/lfsr_counter1/Q_OUT0.CE
L1/lfsr_counter1/Q_OUT0.D
L1/lfsr_counter1/Q_OUT1.CE
L1/lfsr_counter1/Q_OUT1.D
L1/lfsr_counter1/Q_OUT2.CE
L1/lfsr_counter1/Q_OUT2.D
L1/lfsr_counter1/Q_OUT3.CE
L1/lfsr_counter1/Q_OUT3.D
L1/lfsr_counter1/Q_OUT4.CE
L1/lfsr_counter1/Q_OUT4.D
L1/lfsr_counter2/Q_OUT0.CE
L1/lfsr_counter2/Q_OUT0.D
L1/lfsr_counter2/Q_OUT1.CE
L1/lfsr_counter2/Q_OUT1.D 10.0
L1/lfsr_counter2/Q_OUT2.CE
L1/lfsr_counter2/Q_OUT2.D 10.0
L1/lfsr_counter2/Q_OUT3.CE
L1/lfsr_counter2/Q_OUT3.D 10.0
L1/lfsr_counter2/Q_OUT4.CE
L1/lfsr_counter2/Q_OUT4.D 10.0
L1/lfsr_counter2/Q_OUT5.CE
L1/lfsr_counter2/Q_OUT5.D 10.0
L1/lfsr_counter2/Q_OUT6.CE
L1/lfsr_counter2/Q_OUT6.D 10.0
L1/lfsr_counter2/Q_OUT7.CE
L1/lfsr_counter2/Q_OUT7.D 11.0 10.0
SYNC.D
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and end at register D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU.
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