vz_ver4.mod

该工程文件实现ARM系统中CPLD的逻辑工作

MODEL
MODEL_VERSION "v1998.8";
DESIGN "vz_ver4";

/* port names and type */
INPUT PIN16 = CLK;
INPUT PIN14 = CLK_RST;
INPUT PIN1 = A22;
INPUT PIN44 = A21;
INPUT PIN43 = A20;
INPUT PIN2 = EXTCE;
INPUT PIN38 = DISPLAY;
INPUT PIN23 = RSTIN;
OUTPUT PIN29 = HPICE;
OUTPUT PIN30 = NICCE;
OUTPUT PIN37 = DON;
OUTPUT PIN27 = RST_VZ;
OUTPUT PIN18 = SYNC;

/* timing arc definitions */
DISPLAY_DON_delay: DELAY DISPLAY DON;
A21_HPICE_delay: DELAY A21 HPICE;
A22_HPICE_delay: DELAY A22 HPICE;
EXTCE_HPICE_delay: DELAY EXTCE HPICE;
A20_HPICE_delay: DELAY A20 HPICE;
A22_NICCE_delay: DELAY A22 NICCE;
A20_NICCE_delay: DELAY A20 NICCE;
EXTCE_NICCE_delay: DELAY EXTCE NICCE;
A21_NICCE_delay: DELAY A21 NICCE;
RSTIN_RST_VZ_delay: DELAY RSTIN RST_VZ;
CLK_SYNC_delay: DELAY CLK SYNC;

/* timing check arc definitions */

ENDMODEL