cpu_mem.v

来自「这是一个Verilog HDL编写的RISC cpu的程序」· Verilog 代码 · 共 12 行

`timescale 1ns/100ps
module cpu_mem(data_inout,addr,read,write);
  inout [15:0] data_inout;
  input [12:0] addr;
  input read,write;
  reg [15:0] memory[0:'h1FFF];
  wire [15:0] data_inout=read? memory[addr]:16'bz;
  always @(posedge write)
    begin
      memory[addr]=data_inout;
    end
endmodule