cpu_clkg.v

来自「这是一个Verilog HDL编写的RISC cpu的程序」· Verilog 代码 · 共 17 行

`timescale 1ns/10ps
module cpu_clkg(fetch,clk2,clk,alu_clk);
  output fetch,clk2,clk,alu_clk;
  reg fetch,clk2,clk;
  parameter period=60;
  assign alu_clk=(fetch|clk2|clk);
  initial
    fork
      clk=0;
      clk2=1;
      fetch=1;
      forever #(period/2) clk=~clk;
      forever #(period) clk2=~clk2;
      forever #(period*2) fetch=~fetch;
    join
endmodule