cpu_register.v

这是一个Verilog HDL编写的RISC cpu的程序

module cpu_register(data_out,clk,reset,en,data_in);
  output [15:0] data_out;
  input [15:0] data_in;
  input clk,reset,en;
  reg [15:0] data_out;
  always @(posedge clk or reset or en)
    if(reset)
      data_out=16'b0;
    else if(en)
      data_out=data_in;
endmodule