cpu_alu.v

来自「这是一个Verilog HDL编写的RISC cpu的程序」· Verilog 代码 · 共 28 行

`timescale 1ns/1ns
module cpu_alu(alu_out,zero,opcode,data_in,accum,clk);
  input [2:0] opcode;
  input [15:0] data_in,accum;
  input clk;
  output [15:0] alu_out;
  output zero;
  reg [15:0] alu_out;
  parameter z_delay=1.5, alu_delay=4.5;
  always @(posedge clk)
    begin
      case(opcode)
        3'b000: #alu_delay alu_out=accum;
        3'b001: #alu_delay alu_out=accum;
        3'b010: #alu_delay alu_out=data_in+accum;
        3'b011: #alu_delay alu_out=data_in&accum;
        3'b100: #alu_delay alu_out=data_in^accum;
        3'b101: #alu_delay alu_out=data_in;
        3'b110: #alu_delay alu_out=accum;
        3'b111: #alu_delay alu_out=accum;
        default: begin
                   $display("unknown opcode");
                   #alu_delay alu_out=16'bx;
                 end
      endcase
    end
    assign #z_delay zero=(accum==0)?1:0;    
endmodule