cpu_pcounter.v

来自「这是一个Verilog HDL编写的RISC cpu的程序」· Verilog 代码 · 共 17 行

module cpu_pcounter(cnt_out,clk,data_in,reset,load);
  input [12:0] data_in;
  input clk,reset,load;
  output [12:0] cnt_out;
  reg [12:0] cnt_out;
  always @(posedge clk or reset)
    if(!reset)
      cnt_out=13'b0;
    else
      if(load==1)
        cnt_out=data_in;
      else
        if(cnt_out==5'h1FFF)
          cnt_out=13'b0;
        else
          cnt_out=cnt_out+1;
endmodule