cpu_top.v

来自「这是一个Verilog HDL编写的RISC cpu的程序」· Verilog 代码 · 共 19 行

`timescale 1ns/1ps
module cpu_top;
  wire reset,load_acc,load_ir,load_pc,halt,zero;
  wire clock,clk2,alu_clock,fetch,inc_pc;
  wire [15:0] alu_out,acc,data,opcode_iraddr;
  wire [12:0] addr,ir_addr,pc_addr;
  wire [2:0] opcode;
  assign {opcode,ir_addr}=opcode_iraddr;
  cpu_register accumulator(accum,clock,alu_out,load_acc,reset);
  cpu_alu alu(alu_out,zero,opcode,data,accum,alu_clock);
  cpu_datactrl data_ctrl(data,alu_out,fetch,mem_r,clk2);
  cpu_mem mem(data,addr,mem_r,mem_w);
  cpu_register instr_register(opcode_iraddr,clock,data,load_ir,reset);
  cpu_sctrl state_ctrl(load_acc,mem_r,mem_w,inc_pc,load_pc,load_ir,
                         halt,opcode,fetch,zero,clock,clk2,reset);
  cpu_pcounter program_counter(pc_addr,inc_pc,ir_addr,reset,load_pc);
  cpu_admux address_mux(addr,pc_addr,ir_addr,fetch);
  cpu_clkg clock_g(fetch,clk2,clk,alu_clock);
endmodule