_primary.vhd

来自「这是一个Verilog HDL编写的RISC cpu的程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity cpu_admux is
    port(
        addr            : out    vl_logic_vector(12 downto 0);
        pc_addr         : in     vl_logic_vector(12 downto 0);
        ir_addr         : in     vl_logic_vector(12 downto 0);
        fetch           : in     vl_logic
    );
end cpu_admux;