_primary.vhd

来自「这是一个Verilog HDL编写的RISC cpu的程序」· VHDL 代码 · 共 30 行

library verilog;
use verilog.vl_types.all;
entity cpu_sctrl is
    generic(
        hlt             : integer := 0;
        skz             : integer := 1;
        add             : integer := 2;
        \And\           : integer := 3;
        \Xor\           : integer := 4;
        lda             : integer := 5;
        sto             : integer := 6;
        jmp             : integer := 7
    );
    port(
        load_acc        : out    vl_logic;
        mem_r           : out    vl_logic;
        mem_w           : out    vl_logic;
        inc_pc          : out    vl_logic;
        load_pc         : out    vl_logic;
        load_ir         : out    vl_logic;
        halt            : out    vl_logic;
        opcode          : in     vl_logic_vector(2 downto 0);
        fetch           : in     vl_logic;
        zero            : in     vl_logic;
        clk             : in     vl_logic;
        clk2            : in     vl_logic;
        reset           : in     vl_logic
    );
end cpu_sctrl;