_primary.vhd

来自「这是一个Verilog HDL编写的RISC cpu的程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity cpu_mem is
    port(
        data_inout      : inout  vl_logic_vector(15 downto 0);
        addr            : in     vl_logic_vector(12 downto 0);
        read            : in     vl_logic;
        write           : in     vl_logic
    );
end cpu_mem;