_primary.vhd

来自「这是一个Verilog HDL编写的RISC cpu的程序」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity cpu_datactrl is
    port(
        data_out        : out    vl_logic_vector(15 downto 0);
        alu_out         : in     vl_logic_vector(15 downto 0);
        fetch           : in     vl_logic;
        mem_r           : in     vl_logic;
        clk             : in     vl_logic
    );
end cpu_datactrl;