sdram64m16.csf.rpt

用FPGA实现SDRAM的操作

  Info: Implemented 17 output pins
  Info: Implemented 156 logic cells
Info: Selected device EP1C6Q240C8 for design sdram64m16
Info: Smart compilation specified to OFF -- SignalProbe information will not be saved
Info: Automatically promoted some destinations of signal clkmain1 to use Global clock in Pin 29
  Info: Destination sdramclk may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal reset_1 to use Global clock in Pin 28
  Info: Destination addr_p3_402d[7]~4 may be non-global or may not use global clock
  Info: Destination addr_p3_402d[7]~64 may be non-global or may not use global clock
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 9.538 ns
  Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X27_Y14; REG Node = 'length_s0_402d[0]'
  Info: 2: + IC(0.447 ns) + CELL(0.292 ns) = 0.739 ns; Loc. = LAB_X27_Y14; COMB Node = 'LessThan_469~97'
  Info: 3: + IC(0.889 ns) + CELL(0.442 ns) = 2.070 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~102'
  Info: 4: + IC(0.297 ns) + CELL(0.442 ns) = 2.809 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~104'
  Info: 5: + IC(0.297 ns) + CELL(0.442 ns) = 3.548 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~109'
  Info: 6: + IC(0.297 ns) + CELL(0.442 ns) = 4.287 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~111'
  Info: 7: + IC(0.297 ns) + CELL(0.442 ns) = 5.026 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~116'
  Info: 8: + IC(0.297 ns) + CELL(0.442 ns) = 5.765 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~95'
  Info: 9: + IC(1.116 ns) + CELL(0.292 ns) = 7.173 ns; Loc. = LAB_X30_Y15; COMB Node = 'i~3768'
  Info: 10: + IC(0.149 ns) + CELL(0.590 ns) = 7.912 ns; Loc. = LAB_X30_Y15; COMB Node = 'i~3780'
  Info: 11: + IC(0.149 ns) + CELL(0.590 ns) = 8.651 ns; Loc. = LAB_X30_Y15; COMB Node = 'i~3162'
  Info: 12: + IC(0.149 ns) + CELL(0.738 ns) = 9.538 ns; Loc. = LAB_X30_Y15; REG Node = 'temp_s0_402d[1]'
  Info: Total cell delay = 5.154 ns
  Info: Total interconnect delay = 4.384 ns
Warning: Timing characteristics of device EP1C6Q240C8 are preliminary
Warning: Found pins functioning as undefined clocks and/or memory enables
  Info: Assuming node clkmain1 is an undefined clock
Info: Clock clkmain1 has Internal fmax of 145.84 MHz between source register length_s0_402d[5] and destination register length_s0_402d[5] (period= 6.857 ns)
  Info: + Longest register to register delay is 6.596 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y14_N9; REG Node = 'length_s0_402d[5]'
    Info: 2: + IC(1.952 ns) + CELL(0.590 ns) = 2.542 ns; Loc. = LC_X30_Y14_N7; COMB Node = 'i~17712'
    Info: 3: + IC(0.485 ns) + CELL(0.292 ns) = 3.319 ns; Loc. = LC_X30_Y14_N6; COMB Node = 'i~17478'
    Info: 4: + IC(0.740 ns) + CELL(0.590 ns) = 4.649 ns; Loc. = LC_X29_Y14_N7; COMB Node = 'i~7777'
    Info: 5: + IC(1.164 ns) + CELL(0.292 ns) = 6.105 ns; Loc. = LC_X31_Y14_N8; COMB Node = 'i~8104'
    Info: 6: + IC(0.182 ns) + CELL(0.309 ns) = 6.596 ns; Loc. = LC_X31_Y14_N9; REG Node = 'length_s0_402d[5]'
    Info: Total cell delay = 2.073 ns
    Info: Total interconnect delay = 4.523 ns
  Info: - Smallest clock skew is 0.000 ns
    Info: + Shortest clock path from clock clkmain1 to destination register is 2.804 ns
      Info: 1: + IC(0.000 ns) + CELL(1.328 ns) = 1.328 ns; Loc. = Pin_29; CLK Node = 'clkmain1'
      Info: 2: + IC(0.765 ns) + CELL(0.711 ns) = 2.804 ns; Loc. = LC_X31_Y14_N9; REG Node = 'length_s0_402d[5]'
      Info: Total cell delay = 2.039 ns
      Info: Total interconnect delay = 0.765 ns
    Info: - Longest clock path from clock clkmain1 to source register is 2.804 ns
      Info: 1: + IC(0.000 ns) + CELL(1.328 ns) = 1.328 ns; Loc. = Pin_29; CLK Node = 'clkmain1'
      Info: 2: + IC(0.765 ns) + CELL(0.711 ns) = 2.804 ns; Loc. = LC_X31_Y14_N9; REG Node = 'length_s0_402d[5]'
      Info: Total cell delay = 2.039 ns
      Info: Total interconnect delay = 0.765 ns
  Info: + Micro clock to output delay of source is 0.224 ns
  Info: + Micro setup delay of destination is 0.037 ns

+-----------------------------------------------------------------------------+
| Hierarchy                                                                   |
+-----------------------------------------------------------------------------+
Hierarchy
  sdram64m16
    lpm_counter:temp_s0_403d_rtl_0
      alt_counter_stratix:wysi_counter

+-----------------------------------------------------------------------------+
| Logic Options                                                               |
+-----------------------------------------------------------------------------+
+-----------------------------------+-------+
| Name                              | Value |
+-----------------------------------+-------+
| Optimization Technique -- Cyclone | Area  |
| Power-Up Don't Care               | On    |
+-----------------------------------+-------+

+-----------------------------------------------------------------------------+
| Resource Utilization by Entity                                              |
+-----------------------------------------------------------------------------+
+------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------+
| Compilation Hierarchy Node               | Logic Cells | Registers | Memory Bits | DSP Elements | DSP 9x9 | DSP 18x18 | DSP 36x36 | Pins | Virtual Pins | LUT-Only LCs | Register-Only LCs | LUT/Register LCs | Full Hierarchy Name                                                         |
+------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------+
| |sdram64m16                              | 156 (146)   | 51        | 0           | 0            | 0       | 0         | 0         | 47   | 0            | 105 (105)    | 2 (2)             | 49 (39)          | |sdram64m16                                                                 |
|    |lpm_counter:temp_s0_403d_rtl_0|      | 10 (0)      | 10        | 0           | 0            | 0       | 0         | 0         | 0    | 0            | 0 (0)        | 0 (0)             | 10 (0)           | |sdram64m16|lpm_counter:temp_s0_403d_rtl_0                                  |
|       |alt_counter_stratix:wysi_counter| | 10 (10)     | 10        | 0           | 0            | 0       | 0         | 0         | 0    | 0            | 0 (0)        | 0 (0)             | 10 (10)          | |sdram64m16|lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter |
+------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------+

+-----------------------------------------------------------------------------+
| Device Options                                                              |
+-----------------------------------------------------------------------------+
+------------------------------------------------------------------+--------------------------+
| Option                                                           | Setting                  |
+------------------------------------------------------------------+--------------------------+
| Auto-restart configuration after error                           | Off                      |
| Release clears before tri-states                                 | Off                      |
| Enable user-supplied start-up clock (CLKUSR)                     | Off                      |
| Enable device-wide reset (DEV_CLRn)                              | Off                      |
| Enable device-wide output enable (DEV_OE)                        | Off                      |
| Enable INIT_DONE output                                          | Off                      |
| Auto-increment JTAG user code for multiple configuration devices | On                       |
| Disable CONF_DONE and nSTATUS pull-ups on configuration device   | Off                      |
| Generate compressed bitstreams                                   | Off                      |
| Generate Tabular Text File (.ttf)                                | Off                      |
| Generate Raw Binary File (.rbf)                                  | Off                      |
| Generate Hexadecimal Output File (.hexout)                       | Off                      |
| Configuration scheme                                             | Passive Serial           |
| Hexadecimal Output File count direction                          | Up                       |
| Hexadecimal Output File start address                            | 0                        |
| Reserve all unused pins                                          | As output driving ground |
| Configuration device                                             | EPC2                     |
| Base pin-out file on sameframe device                            | Off                      |
| Auto user code                                                   | Off                      |
| Configuration device auto user code                              | Off                      |
| JTAG user code for target device                                 | 0XFFFFFFFF               |
| JTAG user code for configuration device                          | 0XFFFFFFFF               |
+------------------------------------------------------------------+--------------------------+

+-----------------------------------------------------------------------------+
| Equations                                                                   |
+-----------------------------------------------------------------------------+
The equations can be found in D:\all_work\standard\sdram4m16_L2_42\sdram64m16.eqn.htm.

+-----------------------------------------------------------------------------+
| Floorplan View                                                              |
+-----------------------------------------------------------------------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.

+-----------------------------------------------------------------------------+
| Pin-Out File                                                                |
+-----------------------------------------------------------------------------+
The pin-out file can be found in D:\all_work\standard\sdram4m16_L2_42\sdram64m16.pin.

+-----------------------------------------------------------------------------+
| Resource Usage Summary                                                      |
+-----------------------------------------------------------------------------+
+----------------------------+----------------------+
| Resource                   | Usage                |
+----------------------------+----------------------+
| Logic cells                | 155 / 5,980 ( 2 % )  |
| Registers                  | 51 / 6,535 ( < 1 % ) |
| User inserted logic cells  | 0                    |
| I/O pins                   | 47 / 185 ( 25 % )    |
| Clock pins                 | 2                    |
| Dedicated input pins       | 0                    |
| Global signals             | 2                    |
| M4Ks                       | 0 / 20 ( 0 % )       |
| Total memory bits          | 0 / 92,160 ( 0 % )   |
| Total RAM block bits       | 0 / 92,160 ( 0 % )   |
| PLLs                       | 0 / 2 ( 0 % )        |
| Global clocks              | 2 / 8 ( 25 % )       |
| Maximum fan-out node       | clkmain1             |
| Maximum fan-out            | 52                   |