sdram64m16.eqn

用FPGA实现SDRAM的操作

--A1L341 is i~17493 at LC_X28_Y17_N5
--operation mode is normal

A1L341 = temp_s0_402d[0] & !temp_s0_402d[1] & reduce_nor_295;


--A1L521 is i~9821 at LC_X28_Y14_N8
--operation mode is normal

A1L521 = length_s0_402d[0] & (A1L971 # A1L321 # !A1L341);


--A1L431 is i~17475 at LC_X29_Y14_N6
--operation mode is normal

A1L431 = !A1L041 & !A1L441 & A1L341 & A1L761;


--A1L421 is i~9819 at LC_X27_Y14_N6
--operation mode is normal

A1L421 = A1L521 # A1L3 & !A1L971 & A1L431;


--A1L731 is i~17478 at LC_X30_Y14_N6
--operation mode is normal

A1L731 = !temp_s0_402d[0] & temp_s0_402d[1] & A1L551 & A1L651;


--A1L98 is i~4474 at LC_X27_Y14_N9
--operation mode is normal

A1L98 = A1L731 & A1L3 # !A1L731 & length_s0_402d[0];


--A1L17 is addr_p3_402d[7]~64 at LC_X29_Y15_N2
--operation mode is normal

A1L17 = reset_1 & (temp0_s0_401u[3] # temp0_s0_401u[2]);


--A1L021 is i~9404 at LC_X27_Y14_N3
--operation mode is normal

A1L021 = !A1L441 & (A1L11 # !A1L141);


--A1L221 is i~9409 at LC_X27_Y14_N4
--operation mode is normal

A1L221 = length_s0_402d[1] & (A1L971 # A1L021 # !A1L341);


--A1L121 is i~9407 at LC_X27_Y14_N5
--operation mode is normal

A1L121 = A1L221 # A1L11 & !A1L971 & A1L431;


--A1L88 is i~4456 at LC_X27_Y14_N8
--operation mode is normal

A1L88 = length_s0_402d[1] & (A1L11 # !A1L731) # !length_s0_402d[1] & A1L731 & A1L11;


--A1L711 is i~8992 at LC_X28_Y14_N2
--operation mode is normal

A1L711 = !A1L441 & (A1L91 # !A1L141);


--A1L911 is i~8997 at LC_X28_Y14_N3
--operation mode is normal

A1L911 = length_s0_402d[2] & (A1L971 # A1L711 # !A1L341);


--A1L811 is i~8995 at LC_X28_Y14_N4
--operation mode is normal

A1L811 = A1L911 # A1L431 & !A1L971 & A1L91;


--A1L78 is i~4438 at LC_X27_Y14_N1
--operation mode is normal

A1L78 = length_s0_402d[2] & (A1L91 # !A1L731) # !length_s0_402d[2] & A1L731 & A1L91;


--A1L211 is i~7777 at LC_X29_Y14_N7
--operation mode is normal

A1L211 = A1L731 & (A1L481 # A1L431) # !A1L731 & !A1L481 & A1L431;


--A1L111 is i~7765 at LC_X28_Y14_N0
--operation mode is normal

A1L111 = A1L481 # !A1L441 & !A1L141 # !A1L341;


--A1L611 is i~8748 at LC_X29_Y14_N8
--operation mode is normal

A1L611 = A1L72 & (A1L211 # length_s0_402d[3] & A1L111) # !A1L72 & length_s0_402d[3] & A1L111;


--A1L511 is i~8426 at LC_X28_Y14_N5
--operation mode is normal

A1L511 = A1L33 & (A1L211 # length_s0_402d[4] & A1L111) # !A1L33 & length_s0_402d[4] & A1L111;


--A1L411 is i~8104 at LC_X31_Y14_N8
--operation mode is normal

A1L411 = length_s0_402d[5] & (A1L111 # A1L73 & A1L211) # !length_s0_402d[5] & A1L73 & A1L211;


--A1L311 is i~7782 at LC_X30_Y14_N0
--operation mode is normal

A1L311 = A1L54 & (A1L211 # length_s0_402d[6] & A1L111) # !A1L54 & length_s0_402d[6] & A1L111;


--A1L011 is i~7460 at LC_X30_Y14_N2
--operation mode is normal

A1L011 = length_s0_402d[7] & (A1L111 # A1L211 & A1L35) # !length_s0_402d[7] & A1L211 & A1L35;


--refreshack_s1_402d is refreshack_s1_402d at LC_X30_Y16_N0
--operation mode is normal

refreshack_s1_402d_lut_out = refreshack_s1_402d & (!A1L531 # !A1L131) # !refreshack_s1_402d & !temp_s0_402d[1] & !A1L131 & A1L531;
refreshack_s1_402d = DFFEA(refreshack_s1_402d_lut_out, GLOBAL(clkmain1), GLOBAL(reset_1), , , );


--A1L981 is reduce_nor_844~21 at LC_X30_Y16_N4
--operation mode is normal

A1L981 = C1_safe_q[1] # C1_safe_q[0] # C1_safe_q[2] # C1_safe_q[3];


--A1L881 is reduce_nor_844~8 at LC_X31_Y15_N4
--operation mode is normal

A1L881 = C1_safe_q[9] & C1_safe_q[8] & C1_safe_q[7] & C1_safe_q[6];


--A1L781 is reduce_nor_844~0 at LC_X31_Y15_N5
--operation mode is normal

A1L781 = C1_safe_q[5] & C1_safe_q[4] & A1L881;


--temp2_s0_401u[1] is temp2_s0_401u[1] at LC_X29_Y17_N2
--operation mode is normal

temp2_s0_401u[1]_lut_out = !refreshask_s1_404u & !A1L081 & (!xread_1 # !xwrite_1);
temp2_s0_401u[1] = DFFEA(temp2_s0_401u[1]_lut_out, GLOBAL(clkmain1), GLOBAL(reset_1), A1L661, , );


--temp2_s0_401u[0] is temp2_s0_401u[0] at LC_X29_Y16_N6
--operation mode is normal

temp2_s0_401u[0]_lut_out = xread_1 & !temp3_s0_401u[0] & A1L48 # !xread_1 & (A1L541 # !temp3_s0_401u[0] & A1L48);
temp2_s0_401u[0] = DFFEA(temp2_s0_401u[0]_lut_out, GLOBAL(clkmain1), GLOBAL(reset_1), A1L661, , );


--temp2_s0_401u[2] is temp2_s0_401u[2] at LC_X29_Y17_N9
--operation mode is normal

temp2_s0_401u[2]_lut_out = temp3_s0_401u[2] # !A1L081 & (!A1L931 # !xwrite_1);
temp2_s0_401u[2] = DFFEA(temp2_s0_401u[2]_lut_out, GLOBAL(clkmain1), GLOBAL(reset_1), A1L661, , );


--A1L131 is i~14160 at LC_X30_Y16_N9
--operation mode is normal

A1L131 = temp_s0_402d[1] & !temp0_s0_401u[2] & !temp_s0_402d[0] # !temp_s0_402d[1] & (temp_s0_402d[0] # !temp0_s0_401u[2]);


--A1L48 is i~3450 at LC_X29_Y16_N7
--operation mode is normal

A1L48 = A1L081 # !refreshask_s1_404u & xwrite_1;


--temp3_s0_401u[0] is temp3_s0_401u[0] at LC_X28_Y16_N4
--operation mode is normal

temp3_s0_401u[0]_lut_out = temp3_s0_401u[0] # temp_s0_402d[1] & temp_s0_402d[0];
temp3_s0_401u[0] = DFFEA(temp3_s0_401u[0]_lut_out, GLOBAL(clkmain1), GLOBAL(reset_1), , , );


--temp3_s0_401u[2] is temp3_s0_401u[2] at LC_X29_Y18_N2
--operation mode is normal

temp3_s0_401u[2]_lut_out = temp3_s0_401u[2] # temp_s0_402d[0] & temp_s0_402d[1];
temp3_s0_401u[2] = DFFEA(temp3_s0_401u[2]_lut_out, GLOBAL(clkmain1), GLOBAL(reset_1), , , );


--clkmain1 is clkmain1 at Pin_29
--operation mode is input

clkmain1 = INPUT();


--xlength_3[7] is xlength_3[7] at Pin_160
--operation mode is input

xlength_3[7] = INPUT();


--xlength_3[6] is xlength_3[6] at Pin_156
--operation mode is input

xlength_3[6] = INPUT();


--xlength_3[5] is xlength_3[5] at Pin_158
--operation mode is input

xlength_3[5] = INPUT();


--xlength_3[4] is xlength_3[4] at Pin_161
--operation mode is input

xlength_3[4] = INPUT();


--xlength_3[3] is xlength_3[3] at Pin_143
--operation mode is input

xlength_3[3] = INPUT();


--xlength_3[2] is xlength_3[2] at Pin_159
--operation mode is input

xlength_3[2] = INPUT();


--xlength_3[1] is xlength_3[1] at Pin_204
--operation mode is input

xlength_3[1] = INPUT();


--xlength_3[0] is xlength_3[0] at Pin_200
--operation mode is input

xlength_3[0] = INPUT();


--reset_1 is reset_1 at Pin_28
--operation mode is input

reset_1 = INPUT();


--xrasaddr_3[7] is xrasaddr_3[7] at Pin_205
--operation mode is input

xrasaddr_3[7] = INPUT();


--xcasaddr_3[7] is xcasaddr_3[7] at Pin_196
--operation mode is input

xcasaddr_3[7] = INPUT();


--xrasaddr_3[6] is xrasaddr_3[6] at Pin_197
--operation mode is input

xrasaddr_3[6] = INPUT();


--xcasaddr_3[6] is xcasaddr_3[6] at Pin_195
--operation mode is input

xcasaddr_3[6] = INPUT();


--xrasaddr_3[5] is xrasaddr_3[5] at Pin_181
--operation mode is input

xrasaddr_3[5] = INPUT();


--xcasaddr_3[5] is xcasaddr_3[5] at Pin_178
--operation mode is input

xcasaddr_3[5] = INPUT();


--xrasaddr_3[4] is xrasaddr_3[4] at Pin_177
--operation mode is input

xrasaddr_3[4] = INPUT();


--xcasaddr_3[4] is xcasaddr_3[4] at Pin_184
--operation mode is input

xcasaddr_3[4] = INPUT();


--xrasaddr_3[3] is xrasaddr_3[3] at Pin_186
--operation mode is input

xrasaddr_3[3] = INPUT();


--xcasaddr_3[3] is xcasaddr_3[3] at Pin_176
--operation mode is input

xcasaddr_3[3] = INPUT();


--xrasaddr_3[2] is xrasaddr_3[2] at Pin_174
--operation mode is input

xrasaddr_3[2] = INPUT();


--xcasaddr_3[2] is xcasaddr_3[2] at Pin_168
--operation mode is input

xcasaddr_3[2] = INPUT();


--xrasaddr_3[1] is xrasaddr_3[1] at Pin_183
--operation mode is input

xrasaddr_3[1] = INPUT();


--xcasaddr_3[1] is xcasaddr_3[1] at Pin_144
--operation mode is input

xcasaddr_3[1] = INPUT();


--xrasaddr_3[0] is xrasaddr_3[0] at Pin_187
--operation mode is input

xrasaddr_3[0] = INPUT();


--xcasaddr_3[0] is xcasaddr_3[0] at Pin_180
--operation mode is input

xcasaddr_3[0] = INPUT();


--xrasaddr_3[8] is xrasaddr_3[8] at Pin_167
--operation mode is input

xrasaddr_3[8] = INPUT();


--xrasaddr_3[9] is xrasaddr_3[9] at Pin_198
--operation mode is input

xrasaddr_3[9] = INPUT();


--xwrite_1 is xwrite_1 at Pin_165
--operation mode is input

xwrite_1 = INPUT();


--xread_1 is xread_1 at Pin_194
--operation mode is input

xread_1 = INPUT();


--sdramclk is sdramclk at Pin_60
--operation mode is output

sdramclk = OUTPUT(clkmain1);


--ready_p1_402d is ready_p1_402d at Pin_164
--operation mode is output

ready_p1_402d = OUTPUT(!A1L771Q);


--cs_p1_402d is cs_p1_402d at Pin_163
--operation mode is output

cs_p1_402d = OUTPUT(!A1L97Q);


--ras_p1_402d is ras_p1_402d at Pin_169
--operation mode is output

ras_p1_402d = OUTPUT(!A1L571Q);


--cas_p1_402d is cas_p1_402d at Pin_170
--operation mode is output

cas_p1_402d = OUTPUT(!A1L67Q);


--addr_p3_402d[7] is addr_p3_402d[7] at Pin_201
--operation mode is output

addr_p3_402d[7] = OUTPUT(A1L27Q);


--addr_p3_402d[6] is addr_p3_402d[6] at Pin_199
--operation mode is output

addr_p3_402d[6] = OUTPUT(A1L86Q);


--addr_p3_402d[5] is addr_p3_402d[5] at Pin_173
--operation mode is output

addr_p3_402d[5] = OUTPUT(A1L66Q);


--addr_p3_402d[4] is addr_p3_402d[4] at Pin_188
--operation mode is output

addr_p3_402d[4] = OUTPUT(A1L46Q);


--addr_p3_402d[3] is addr_p3_402d[3] at Pin_185
--operation mode is output

addr_p3_402d[3] = OUTPUT(A1L26Q);


--addr_p3_402d[2] is addr_p3_402d[2] at Pin_175
--operation mode is output

addr_p3_402d[2] = OUTPUT(A1L06Q);


--addr_p3_402d[1] is addr_p3_402d[1] at Pin_182
--operation mode is output

addr_p3_402d[1] = OUTPUT(A1L85Q);


--addr_p3_402d[0] is addr_p3_402d[0] at Pin_179
--operation mode is output

addr_p3_402d[0] = OUTPUT(A1L65Q);


--a8_p0_402d is a8_p0_402d at Pin_166
--operation mode is output

a8_p0_402d = OUTPUT(A1L2Q);


--ba_p3_402d is ba_p3_402d at Pin_202
--operation mode is output

ba_p3_402d = OUTPUT(A1L47Q);


--we_p1_402d is we_p1_402d at Pin_193
--operation mode is output

we_p1_402d = OUTPUT(!A1L612Q);


--dqm_p3_402d is dqm_p3_402d at Pin_162
--operation mode is output

dqm_p3_402d = OUTPUT(!A1L18Q);