mix_scr.prd

Verilog&Vhdl混语言对SDRAM的控制源代码

#-- Synplicity, Inc.
#-- Version 7.2        
#-- Project file J:\temp\Synplify_Pro\Mix\Mix_scr.prd
#-- Written on Thu Dec 19 18:06:58 2002

#
### Watch Implementation type ###
#
watch_impl -active
#
### Watch Implementation properties ###
#
watch_prop -clear { sdrm I/O primitives } { sdrm I/O Register bits } { sdrm Total Luts } {  Worst Slack } {  sdrm|Clk0A_derived_clock - Slack }