unisim.vhd

来自「Verilog&Vhdl混语言对SDRAM的控制源代码」· VHDL 代码 · 共 2,782 行 · 第 1/5 页

VHD
2,782 行
字号
12345
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_2 : component is true;
component IOBUF_F_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_24 : component is true;
component IOBUF_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_4 : component is true;
component IOBUF_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_6 : component is true;
component IOBUF_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_8 : component is true;
component IOBUF_GTL
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTL : component is true;
component IOBUF_GTL_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTL_DCI : component is true;
component IOBUF_GTLP
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTLP : component is true;
component IOBUF_GTLP_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTLP_DCI : component is true;
component IOBUF_HSTL_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_I : component is true;
component IOBUF_HSTL_I_18
  port (
  O : out std_logic;
  IO : inout std_logic;
  I : in std_logic;
  T : in std_logic
  );
end component;
attribute syn_black_box of IOBUF_HSTL_I_18 : component is true;
component IOBUF_HSTL_I_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_I_DCI : component is true;
component IOBUF_HSTL_II
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_II : component is true;
component IOBUF_HSTL_II_18
  port (
    O : out std_logic;
    IO : inout std_logic;
    I : in std_logic;
    T : in std_logic
  );
end component;
attribute syn_black_box of IOBUF_HSTL_II_18 : component is true;
component IOBUF_HSTL_II_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_II_DCI : component is true;
component IOBUF_HSTL_II_DCI_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_II_DCI_18 : component is true;
component IOBUF_HSTL_III
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_III : component is true;
component IOBUF_HSTL_III_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_III_18 : component is true;
component IOBUF_HSTL_III_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_III_DCI : component is true;
component IOBUF_HSTL_III_DCI_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_III_DCI_18 : component is true;
component IOBUF_HSTL_IV
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_IV : component is true;
component IOBUF_HSTL_IV_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_IV_18 : component is true;
component IOBUF_HSTL_IV_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_IV_DCI : component is true;
component IOBUF_HSTL_IV_DCI_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_IV_DCI_18 : component is true;
component IOBUF_LVCMOS15
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15 : component is true;
component IOBUF_LVCMOS15_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_12 : component is true;
component IOBUF_LVCMOS15_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_16 : component is true;
component IOBUF_LVCMOS15_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_2 : component is true;
component IOBUF_LVCMOS15_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_4 : component is true;
component IOBUF_LVCMOS15_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_6 : component is true;
component IOBUF_LVCMOS15_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_8 : component is true;
component IOBUF_LVCMOS15_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_12 : component is true;
component IOBUF_LVCMOS15_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_16 : component is true;
component IOBUF_LVCMOS15_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_2 : component is true;
component IOBUF_LVCMOS15_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_4 : component is true;
component IOBUF_LVCMOS15_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_6 : component is true;
component IOBUF_LVCMOS15_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_8 : component is true;
component IOBUF_LVCMOS18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18 : component is true;
component IOBUF_LVCMOS18_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_12 : component is true;
component IOBUF_LVCMOS18_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_16 : component is true;
component IOBUF_LVCMOS18_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_2 : component is true;
component IOBUF_LVCMOS18_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_4 : component is true;
component IOBUF_LVCMOS18_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_6 : component is true;
component IOBUF_LVCMOS18_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_8 : component is true;
component IOBUF_LVCMOS18_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_12 : component is true;
component IOBUF_LVCMOS18_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_16 : component is true;
component IOBUF_LVCMOS18_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_2 : component is true;
component IOBUF_LVCMOS18_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_4 : component is true;
component IOBUF_LVCMOS18_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_6 : component is true;
component IOBUF_LVCMOS18_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_8 : component is true;
component IOBUF_LVCMOS2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS2 : component is true;
component IOBUF_LVCMOS25
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25 : component is true;
component IOBUF_LVCMOS25_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_12 : component is true;
component IOBUF_LVCMOS25_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_16 : component is true;
component IOBUF_LVCMOS25_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_2 : component is true;
component IOBUF_LVCMOS25_F_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_24 : component is true;
component IOBUF_LVCMOS25_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_4 : component is true;
component IOBUF_LVCMOS25_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_6 : component is true;
component IOBUF_LVCMOS25_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_8 : component is true;
component IOBUF_LVCMOS25_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_12 : component is true;
component IOBUF_LVCMOS25_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_16 : component is true;
component IOBUF_LVCMOS25_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_2 : component is true;
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unisim.vhd - 源码说明

本页面展示了「Verilog&Vhdl混语言对SDRAM的控制源代码」中的 unisim.vhd 源码文件，采用 VHDL 编程语言编写，共 2,782 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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