4ex.tim

来自「Verilog&Vhdl混语言对SDRAM的控制源代码」· TIM 代码 · 共 18 行

#
# 4ex.tim
#$Header: /syn/cvs/rcs/mappers/xilinx/lib/4ex.tim,v 1.2 1999/06/01 17:18:00 naresh Exp $
#
@EN#0s00_OVD_HRDC
0#CR8NM_N#ODjCR3#c
CG0RF#s_OCNDR6j3
0#CRGlk_N#ODjCR3yn
RbONboHMRVFVRC0ERksF00CRNCLDRRN0(R3jM0#RFPRNFRH8DoNsCCR8D#N$RsVFRsIHCI#RHR0EP$CsRoEHENRVM0Fk#>R5Rj4jj#2
CF0sk00CNCLDR3"4g3,.d3,.(3,d.3,d63,dU3,c43,cd3,c63,c(3,cg3,643,6.3,6d3,6c3,663,6n3,6(3,6U3,6g3,nj3,n43,n.3,nd3,nc3,n63,nn3,n(3,nU3,ng3,(j3,(jy"
R8N8HF0HMRNDs0FkHRMoVlsFRmQ/RMbH#RR-#DONCL8R$FRsk_0C#DONCC
#0sbNlFRsk_0CHkMb0.RR3#U
CN0bsslRFCk0_0FkbRk0.
3UC_M80_ODVCHDR