coolrunner2.vhd

来自「Verilog&Vhdl混语言对SDRAM的控制源代码」· VHDL 代码 · 共 1,474 行 · 第 1/3 页

 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NAND5B2 : component is true;
component NAND5B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NAND5B3 : component is true;
component NAND5B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NAND5B4 : component is true;
component NAND5B5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NAND5B5 : component is true;
component NAND6
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic
 );
end component;
attribute syn_black_box of NAND6 : component is true;
component NAND7
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic
 );
end component;
attribute syn_black_box of NAND7 : component is true;
component NAND8
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic
 );
end component;
attribute syn_black_box of NAND8 : component is true;
component NAND9
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic;
   I8 : in std_logic
 );
end component;
attribute syn_black_box of NAND9 : component is true;
component NOR2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of NOR2 : component is true;
component NOR2B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of NOR2B1 : component is true;
component NOR2B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of NOR2B2 : component is true;
component NOR3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NOR3 : component is true;
component NOR3B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NOR3B1 : component is true;
component NOR3B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NOR3B2 : component is true;
component NOR3B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NOR3B3 : component is true;
component NOR4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4 : component is true;
component NOR4B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4B1 : component is true;
component NOR4B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4B2 : component is true;
component NOR4B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4B3 : component is true;
component NOR4B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4B4 : component is true;
component NOR5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5 : component is true;
component NOR5B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B1 : component is true;
component NOR5B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B2 : component is true;
component NOR5B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B3 : component is true;
component NOR5B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B4 : component is true;
component NOR5B5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B5 : component is true;
component NOR6
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic
 );
end component;
attribute syn_black_box of NOR6 : component is true;
component NOR7
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic
 );
end component;
attribute syn_black_box of NOR7 : component is true;
component NOR8
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic
 );
end component;
attribute syn_black_box of NOR8 : component is true;
component NOR9
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic;
   I8 : in std_logic
 );
end component;
attribute syn_black_box of NOR9 : component is true;
component OBUF
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF : component is true;
attribute black_box_pad_pin of OBUF : component is "O";
component OBUFE
 port (
   O : out std_logic;
   E : in std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUFE : component is true;
attribute black_box_pad_pin of OBUFE : component is "O";
attribute black_box_tri_pins of OBUFE : component is "O";
component OBUFT
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT : component is true;
attribute black_box_pad_pin of OBUFT : component is "O";
attribute black_box_tri_pins of OBUFT : component is "O";
component OR2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of OR2 : component is true;
component OR2B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of OR2B1 : component is true;
component OR2B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of OR2B2 : component is true;
component OR3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of OR3 : component is true;
component OR3B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of OR3B1 : component is true;
component OR3B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of OR3B2 : component is true;
component OR3B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of OR3B3 : component is true;
component OR4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4 : component is true;
component OR4B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4B1 : component is true;
component OR4B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4B2 : component is true;
component OR4B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4B3 : component is true;
component OR4B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4B4 : component is true;
component OR5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5 : component is true;
component OR5B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B1 : component is true;
component OR5B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;