4ex-4.tim

Verilog&Vhdl混语言对SDRAM的控制源代码

#
# 4ex-4.tim
#$Header: /syn/cvs/rcs/mappers/xilinx/lib/4ex-4.tim,v 1.2 1999/07/29 23:40:49 naresh Exp $
#
@EN#0s00_OVD_HRDC
0#CRNVlbC_8D3R..C
#0sbNllRVN8b_CfDRVblN_D8C
0#CblNsRlVEN8b_CdDR3#U
CN0bsElRl_Nb8RCDd
3j#bC0NRslVblN_0#CRc43
0#CblNsRlVEN#b_Cd0R3#.
CN0bs8lR_0#CRd43
0#CblNsR_CM#RC04
36#bC0NRslVOV_J3R..C
#0sbNlHROO8F_CjDR3#6
CN0bsOlRHNVlbC_8D3Rc(C
#0sbNlMRHHF0O_D8CR.d3
0#CblNsRF8O_D8CR(c3
0#CblNsR_N#8RCDR6c3
0#CblNsRkHLVC_8D0_0D3R..#R
CN0bsHlRL_kV8_CDO#lFR..3
0#CblNsRkFLVC_8D__V0R0Dn
3.#bC0NRslFVLk_D8C_OV_lRF#n
3.#bC0NRslFVLk_D8C_0#_0nDR3#.
CN0bsFlRL_kV8_CD#l_OFn#R3#.
CN0bsFlRL_kVCVM__D00R.n3
0#CblNsRkFLVM_C_0#_0nDR3#.
CN0bsFlRL_kVCVM__FOl#3Rn.C
#0sbNlLRFkCV_M__#O#lFR.n3
0#CblNsRVFV__OJV0_0D3R(cC
#0sbNlVRFVJ_O_OV_lRF#(
3c#bC0NRslF_VVO#J__D00Rc(3
0#CblNsRVFV__OJ#l_OF(#R3
c
#bC0NRslF_VV8C_#03RjnC
#0sbNlVRFVM_C_0#CRjj3
C
#0sbNlMRN8D_8$CRrGRbsfNVlbC_8DRR*f8NM_N#OD
C9#bC0NRslG_Fs8RD$rbCGsVRfl_Nb8RCD*GRfF#s_OCND9C
#0sbNlkRlGD_8$CRrGRbsfNVlbC_8DRR*fGlk_N#OD
C9
0#CblNsRksF0#C_OCNDRj43
NyRbFbsGNHl0#CROHNDMFoRVqR)vHR0loHMRlMkL#CsRFVslpRXq(-j
0#CblNsRD#CC_O0s_Nl#DONC3R.jCj
M08_OVD_HRDC