vgacore.vhd

VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vgacore is
    Port ( clk : in std_logic;
	        reset : in std_logic;
           md : in std_logic_vector(1 downto 0);
           hs : out std_logic;
           vs : out std_logic;
           r : out std_logic;
           g : out std_logic;
           b : out std_logic);
end vgacore;

architecture Behavioral of vgacore is
signal sysclk : std_logic;
--signal div_count : std_logic_vector(1 downto 0);
signal hsyncb : std_logic;
signal vsyncb : std_logic;
signal enable : std_logic;
signal hloc : std_logic_vector(9 downto 0);
signal vloc : std_logic_vector(9 downto 0);
signal rgbx,rgby,rgbp,rgb: std_logic_vector(2 downto 0);
--signal mmd : std_logic_vector(1 downto 0);

component vgasig 
   Port (
       clock : in std_logic;
       reset : in std_logic;
       hsyncb : buffer std_logic;
       vsyncb : out std_logic;
       enable : out std_logic;
       Xaddr : out std_logic_vector(9 downto 0);
       Yaddr : out std_logic_vector(9 downto 0)
	 );
end component;

component colormap 
   Port (
       hloc : in std_logic_vector(9 downto 0);
       vloc : in std_logic_vector(9 downto 0);
       rgbx : out std_logic_vector(2 downto 0);
       rgby : out std_logic_vector(2 downto 0)
	 );
end component;

begin
  rgb(2) <= rgbp(2) and enable;
  rgb(1) <= rgbp(1) and enable;
  rgb(0) <= rgbp(0) and enable;

  divclk: process(clk,reset)
  begin
    if reset='0' then
 	   sysclk <= '0';
	 elsif clk'event and clk='1' then
	   sysclk <= not sysclk;
	 end if;
  end process;
  
  modchoice: process(md,rgbx,rgby)
  begin
    if md="11" then rgbp <= rgbx;
	 elsif md="01" then rgbp <= rgby;
	 elsif md="10" then rgbp <= rgbx xor rgby;
    else rgbp <= "000";
	 end if;
  end process;

  makesig: vgasig Port map(
       clock => sysclk,
       reset => reset,
       hsyncb => hsyncb,
       vsyncb => vsyncb,
       enable => enable,
       Xaddr => hloc,
       Yaddr => vloc
	 );

  makergb: colormap Port map(
       hloc => hloc,
       vloc => vloc,
       rgbx => rgbx,
       rgby => rgby
  );

  hs <= hsyncb;
  vs <= vsyncb;
  r <= rgb(2);
  g <= rgb(1);
  b <= rgb(0);
   
end Behavioral;