📄 fifoasi.qsf
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# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
# The default values for assignments are stored in the file
# fifoasi_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:13:03 AUGUST 30, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name BDF_FILE 16to8ddf.bdf
set_global_assignment -name BDF_FILE 8to16ddf.bdf
set_global_assignment -name VERILOG_FILE Q32.v
set_global_assignment -name VERILOG_FILE INT.v
set_global_assignment -name VERILOG_FILE uncode.v
set_global_assignment -name VERILOG_FILE asitodsp.v
set_global_assignment -name VERILOG_FILE dsptoasi.v
set_global_assignment -name BDF_FILE fifo_asi.bdf
set_global_assignment -name VERILOG_FILE control.v
set_global_assignment -name VECTOR_WAVEFORM_FILE ../VWFA/VWFA.vwf
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_U3 -to RXSTA0
set_location_assignment PIN_V4 -to RXSTA1
set_location_assignment PIN_T4 -to RXSTA2
set_location_assignment PIN_U4 -to RXDA\[0\]
set_location_assignment PIN_T5 -to RXDA\[1\]
set_location_assignment PIN_U5 -to RXDA\[2\]
set_location_assignment PIN_N8 -to RXDA\[3\]
set_location_assignment PIN_M8 -to RXDA\[4\]
set_location_assignment PIN_V6 -to RXDA\[5\]
set_location_assignment PIN_U6 -to RXDA\[6\]
set_location_assignment PIN_P6 -to RXDA\[7\]
set_location_assignment PIN_T8 -to TXCTA0
set_location_assignment PIN_V8 -to TXCTABCD\[0\]
set_location_assignment PIN_U8 -to TXDA\[0\]
set_location_assignment PIN_R7 -to TXDA\[1\]
set_location_assignment PIN_T7 -to TXDA\[2\]
set_location_assignment PIN_V7 -to TXDA\[3\]
set_location_assignment PIN_U7 -to TXDA\[4\]
set_location_assignment PIN_R6 -to TXDA\[5\]
set_location_assignment PIN_T6 -to TXDA\[6\]
set_location_assignment PIN_P7 -to TXDA\[7\]
set_location_assignment PIN_U10 -to RXSTB0
set_location_assignment PIN_V10 -to RXSTB1
set_location_assignment PIN_T10 -to RXSTB2
set_location_assignment PIN_R10 -to RXDB\[0\]
set_location_assignment PIN_P10 -to RXDB\[1\]
set_location_assignment PIN_R11 -to RXDB\[2\]
set_location_assignment PIN_T11 -to RXDB\[3\]
set_location_assignment PIN_U11 -to RXDB\[4\]
set_location_assignment PIN_V11 -to RXDB\[5\]
set_location_assignment PIN_V12 -to RXDB\[6\]
set_location_assignment PIN_U12 -to RXDB\[7\]
set_location_assignment PIN_M11 -to TXCTABCD\[1\]
set_location_assignment PIN_N11 -to TXCTB0
set_location_assignment PIN_P12 -to TXDB\[0\]
set_location_assignment PIN_N10 -to TXDB\[1\]
set_location_assignment PIN_M10 -to TXDB\[2\]
set_location_assignment PIN_R13 -to TXDB\[3\]
set_location_assignment PIN_T13 -to TXDB\[4\]
set_location_assignment PIN_U13 -to TXDB\[5\]
set_location_assignment PIN_V13 -to TXDB\[6\]
set_location_assignment PIN_R12 -to TXDB\[7\]
set_location_assignment PIN_D8 -to RXDD\[0\]
set_location_assignment PIN_C8 -to RXDD\[1\]
set_location_assignment PIN_A8 -to RXDD\[2\]
set_location_assignment PIN_B8 -to RXDD\[3\]
set_location_assignment PIN_E8 -to RXDD\[4\]
set_location_assignment PIN_E7 -to RXDD\[5\]
set_location_assignment PIN_A7 -to RXDD\[6\]
set_location_assignment PIN_B7 -to RXDD\[7\]
set_location_assignment PIN_C9 -to RXSTD0
set_location_assignment PIN_A9 -to RXSTD1
set_location_assignment PIN_B9 -to RXSTD2
set_location_assignment PIN_D5 -to TXCTABCD\[3\]
set_location_assignment PIN_A4 -to TXCTD0
set_location_assignment PIN_C5 -to TXDD\[0\]
set_location_assignment PIN_G8 -to TXDD\[1\]
set_location_assignment PIN_F8 -to TXDD\[2\]
set_location_assignment PIN_C6 -to TXDD\[3\]
set_location_assignment PIN_B6 -to TXDD\[4\]
set_location_assignment PIN_D6 -to TXDD\[5\]
set_location_assignment PIN_E6 -to TXDD\[6\]
set_location_assignment PIN_C7 -to TXDD\[7\]
set_location_assignment PIN_A15 -to RXDC\[0\]
set_location_assignment PIN_C15 -to RXDC\[1\]
set_location_assignment PIN_D14 -to RXDC\[2\]
set_location_assignment PIN_B14 -to RXDC\[3\]
set_location_assignment PIN_E13 -to RXDC\[4\]
set_location_assignment PIN_G11 -to RXDC\[5\]
set_location_assignment PIN_F11 -to RXDC\[6\]
set_location_assignment PIN_G10 -to RXDC\[7\]
set_location_assignment PIN_C16 -to RXSTC0
set_location_assignment PIN_B16 -to RXSTC1
set_location_assignment PIN_B15 -to RXSTC2
set_location_assignment PIN_C11 -to TXCTABCD\[2\]
set_location_assignment PIN_D11 -to TXCTC0
set_location_assignment PIN_A12 -to TXDC\[0\]
set_location_assignment PIN_B12 -to TXDC\[1\]
set_location_assignment PIN_C12 -to TXDC\[2\]
set_location_assignment PIN_D12 -to TXDC\[3\]
set_location_assignment PIN_C13 -to TXDC\[4\]
set_location_assignment PIN_D13 -to TXDC\[5\]
set_location_assignment PIN_A13 -to TXDC\[6\]
set_location_assignment PIN_B13 -to TXDC\[7\]
set_location_assignment PIN_T16 -to OUTIO\[0\]
set_location_assignment PIN_T17 -to OUTIO\[1\]
set_location_assignment PIN_R17 -to OUTIO\[2\]
set_location_assignment PIN_R18 -to OUTIO\[3\]
set_location_assignment PIN_R15 -to OUTIO\[4\]
set_location_assignment PIN_R16 -to OUTIO\[5\]
set_location_assignment PIN_P14 -to OUTIO\[6\]
set_location_assignment PIN_N14 -to OUTIO\[7\]
set_location_assignment PIN_N18 -to OUTIO\[8\]
set_location_assignment PIN_N17 -to OUTIO\[9\]
set_location_assignment PIN_N13 -to OUTIO\[10\]
set_location_assignment PIN_N12 -to OUTIO\[11\]
set_location_assignment PIN_N16 -to OUTIO\[12\]
set_location_assignment PIN_N15 -to OUTIO\[13\]
set_location_assignment PIN_M18 -to OUTIO\[14\]
set_location_assignment PIN_M17 -to OUTIO\[15\]
set_location_assignment PIN_H14 -to BOND_INH
set_location_assignment PIN_H15 -to DECMODE
set_location_assignment PIN_G18 -to LPEN
set_location_assignment PIN_H16 -to SDASEL
set_location_assignment PIN_H17 -to TXRST
set_location_assignment PIN_L15 -to BISTLE
set_location_assignment PIN_L13 -to OELE
set_location_assignment PIN_L16 -to RXLE
set_location_assignment PIN_L17 -to RXMODE0
set_location_assignment PIN_L18 -to RXMODE1
set_location_assignment PIN_M13 -to SCSEL
set_location_assignment PIN_M15 -to TXMODE0
set_location_assignment PIN_M14 -to TXMODE1
set_location_assignment PIN_R8 -to INTA
set_location_assignment PIN_U14 -to INTB
set_location_assignment PIN_B11 -to INTC
set_location_assignment PIN_B4 -to INTD
set_location_assignment PIN_M4 -to dspio\[0\]
set_location_assignment PIN_N1 -to dspio\[1\]
set_location_assignment PIN_N2 -to dspio\[2\]
set_location_assignment PIN_M6 -to dspio\[3\]
set_location_assignment PIN_N7 -to dspio\[4\]
set_location_assignment PIN_N5 -to dspio\[5\]
set_location_assignment PIN_N6 -to dspio\[6\]
set_location_assignment PIN_N3 -to dspio\[7\]
set_location_assignment PIN_N4 -to dspio\[8\]
set_location_assignment PIN_P5 -to dspio\[9\]
set_location_assignment PIN_P2 -to dspio\[10\]
set_location_assignment PIN_P3 -to dspio\[11\]
set_location_assignment PIN_R2 -to dspio\[12\]
set_location_assignment PIN_R3 -to dspio\[13\]
set_location_assignment PIN_T2 -to dspio\[14\]
set_location_assignment PIN_T3 -to dspio\[15\]
set_location_assignment PIN_G2 -to BE0
set_location_assignment PIN_G1 -to CE\[0\]
set_location_assignment PIN_F5 -to CE\[1\]
set_location_assignment PIN_F4 -to CE\[2\]
set_location_assignment PIN_F3 -to CE\[3\]
set_location_assignment PIN_F6 -to EA\[0\]
set_location_assignment PIN_F7 -to EA\[1\]
set_location_assignment PIN_G3 -to EA\[2\]
set_location_assignment PIN_G4 -to EA\[3\]
set_location_assignment PIN_G5 -to EA\[4\]
set_location_assignment PIN_G6 -to EA\[5\]
set_location_assignment PIN_H2 -to EA\[6\]
set_location_assignment PIN_H3 -to EA\[7\]
set_location_assignment PIN_H4 -to EA\[8\]
set_location_assignment PIN_H5 -to EA\[9\]
set_location_assignment PIN_L3 -to SYS_RST
set_location_assignment PIN_L2 -to TRSTZ
set_location_assignment PIN_F2 -to SOE3
set_location_assignment PIN_J16 -to ASICLK
set_location_assignment PIN_J4 -to DSPCLK
set_location_assignment PIN_T9 -to LFI\[0\]
set_location_assignment PIN_T12 -to LFI\[1\]
set_location_assignment PIN_F10 -to LFI\[2\]
set_location_assignment PIN_D7 -to LFI\[3\]
# Timing Assignments
# ==================
set_global_assignment -name DO_MIN_ANALYSIS OFF
set_global_assignment -name MIN_TCO_REQUIREMENT 5ns
set_global_assignment -name TPD_REQUIREMENT 15ns
set_global_assignment -name TSU_REQUIREMENT 15ns
set_global_assignment -name TCO_REQUIREMENT 15ns
set_global_assignment -name TH_REQUIREMENT 5ns
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 324
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY fifo_asi
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C4F324C8
set_global_assignment -name DEVICE_MIGRATION_LIST EP1C4F324C8
# Timing Analysis Assignments
# ===========================
set_global_assignment -name MINIMUM_TPD_REQUIREMENT 5ns
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off
# -------------------
# start CLOCK(ASICLK)
# Timing Assignments
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id ASICLK
set_global_assignment -name FMAX_REQUIREMENT "27.0 MHz" -section_id ASICLK
# end CLOCK(ASICLK)
# -----------------
# -------------------
# start CLOCK(DSPCLK)
# Timing Assignments
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id DSPCLK
set_global_assignment -name FMAX_REQUIREMENT "100.0 MHz" -section_id DSPCLK
# end CLOCK(DSPCLK)
# -----------------
# ----------------------
# start ENTITY(fifo_asi)
# Timing Assignments
# ==================
set_instance_assignment -name CLOCK_SETTINGS ASICLK -to ASICLK
set_instance_assignment -name CLOCK_SETTINGS DSPCLK -to DSPCLK
set_instance_assignment -name CLOCK_SETTINGS WCLK -to WCLK
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
# end ENTITY(fifo_asi)
# --------------------
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