dsptoasi.v

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe33a[0:0] <= 1;
		else if (clrn == 1'b0) dffe33a[0:0] <= 0;
		else if  (ena == 1'b1)   dffe33a[0:0] <= wire_dffe33a_D[0:0];
	// synopsys translate_off
	initial
		dffe33a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe33a[1:1] <= 1;
		else if (clrn == 1'b0) dffe33a[1:1] <= 0;
		else if  (ena == 1'b1)   dffe33a[1:1] <= wire_dffe33a_D[1:1];
	// synopsys translate_off
	initial
		dffe33a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe33a[2:2] <= 1;
		else if (clrn == 1'b0) dffe33a[2:2] <= 0;
		else if  (ena == 1'b1)   dffe33a[2:2] <= wire_dffe33a_D[2:2];
	// synopsys translate_off
	initial
		dffe33a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe33a[3:3] <= 1;
		else if (clrn == 1'b0) dffe33a[3:3] <= 0;
		else if  (ena == 1'b1)   dffe33a[3:3] <= wire_dffe33a_D[3:3];
	// synopsys translate_off
	initial
		dffe33a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe33a[4:4] <= 1;
		else if (clrn == 1'b0) dffe33a[4:4] <= 0;
		else if  (ena == 1'b1)   dffe33a[4:4] <= wire_dffe33a_D[4:4];
	// synopsys translate_off
	initial
		dffe33a[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe33a[5:5] <= 1;
		else if (clrn == 1'b0) dffe33a[5:5] <= 0;
		else if  (ena == 1'b1)   dffe33a[5:5] <= wire_dffe33a_D[5:5];
	// synopsys translate_off
	initial
		dffe33a[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe33a[6:6] <= 1;
		else if (clrn == 1'b0) dffe33a[6:6] <= 0;
		else if  (ena == 1'b1)   dffe33a[6:6] <= wire_dffe33a_D[6:6];
	// synopsys translate_off
	initial
		dffe33a[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe33a[7:7] <= 1;
		else if (clrn == 1'b0) dffe33a[7:7] <= 0;
		else if  (ena == 1'b1)   dffe33a[7:7] <= wire_dffe33a_D[7:7];
	assign
		wire_dffe33a_D = (dffe32a & {8{(~ sclr)}});
	// synopsys translate_off
	initial
		dffe34a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe34a[0:0] <= 1;
		else if (clrn == 1'b0) dffe34a[0:0] <= 0;
		else if  (ena == 1'b1)   dffe34a[0:0] <= wire_dffe34a_D[0:0];
	// synopsys translate_off
	initial
		dffe34a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe34a[1:1] <= 1;
		else if (clrn == 1'b0) dffe34a[1:1] <= 0;
		else if  (ena == 1'b1)   dffe34a[1:1] <= wire_dffe34a_D[1:1];
	// synopsys translate_off
	initial
		dffe34a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe34a[2:2] <= 1;
		else if (clrn == 1'b0) dffe34a[2:2] <= 0;
		else if  (ena == 1'b1)   dffe34a[2:2] <= wire_dffe34a_D[2:2];
	// synopsys translate_off
	initial
		dffe34a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe34a[3:3] <= 1;
		else if (clrn == 1'b0) dffe34a[3:3] <= 0;
		else if  (ena == 1'b1)   dffe34a[3:3] <= wire_dffe34a_D[3:3];
	// synopsys translate_off
	initial
		dffe34a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe34a[4:4] <= 1;
		else if (clrn == 1'b0) dffe34a[4:4] <= 0;
		else if  (ena == 1'b1)   dffe34a[4:4] <= wire_dffe34a_D[4:4];
	// synopsys translate_off
	initial
		dffe34a[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe34a[5:5] <= 1;
		else if (clrn == 1'b0) dffe34a[5:5] <= 0;
		else if  (ena == 1'b1)   dffe34a[5:5] <= wire_dffe34a_D[5:5];
	// synopsys translate_off
	initial
		dffe34a[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe34a[6:6] <= 1;
		else if (clrn == 1'b0) dffe34a[6:6] <= 0;
		else if  (ena == 1'b1)   dffe34a[6:6] <= wire_dffe34a_D[6:6];
	// synopsys translate_off
	initial
		dffe34a[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clock or negedge prn or negedge clrn)
		if (prn == 1'b0) dffe34a[7:7] <= 1;
		else if (clrn == 1'b0) dffe34a[7:7] <= 0;
		else if  (ena == 1'b1)   dffe34a[7:7] <= wire_dffe34a_D[7:7];
	assign
		wire_dffe34a_D = (dffe33a & {8{(~ sclr)}});
	assign
		ena = 1'b1,
		prn = 1'b1,
		q = dffe34a,
		sclr = 1'b0;
endmodule //dsptoasi_dffpipe_2a3

//synthesis_resources = lut 24 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  dsptoasi_alt_synch_pipe_2a3
	( 
	clock,
	clrn,
	d,
	q) /* synthesis synthesis_clearbox=1 */
		/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
	input   clock;
	input   clrn;
	input   [7:0]  d;
	output   [7:0]  q;

	wire  [7:0]   wire_dffpipe31_q;

	dsptoasi_dffpipe_2a3   dffpipe31
	( 
	.clock(clock),
	.clrn(clrn),
	.d(d),
	.q(wire_dffpipe31_q));
	assign
		q = wire_dffpipe31_q;
endmodule //dsptoasi_alt_synch_pipe_2a3


//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=8 dataa datab result
//VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ  VERSION_END

//synthesis_resources = lut 8 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  dsptoasi_add_sub_008
	( 
	dataa,
	datab,
	result) /* synthesis synthesis_clearbox=1 */;
	input   [7:0]  dataa;
	input   [7:0]  datab;
	output   [7:0]  result;

	wire  [7:0]   wire_add_sub_cella_combout;
	wire  [0:0]   wire_add_sub_cella_0cout;
	wire  [0:0]   wire_add_sub_cella_1cout;
	wire  [0:0]   wire_add_sub_cella_2cout;
	wire  [0:0]   wire_add_sub_cella_3cout;
	wire  [0:0]   wire_add_sub_cella_4cout;
	wire  [0:0]   wire_add_sub_cella_5cout;
	wire  [0:0]   wire_add_sub_cella_6cout;
	wire  [7:0]   wire_add_sub_cella_dataa;
	wire  [7:0]   wire_add_sub_cella_datab;

	cyclone_lcell   add_sub_cella_0
	( 
	.cin(1'b1),
	.combout(wire_add_sub_cella_combout[0:0]),
	.cout(wire_add_sub_cella_0cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[0:0]),
	.datab(wire_add_sub_cella_datab[0:0]),
	.regout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.clk(1'b1),
	.datac(1'b1),
	.datad(1'b1),
	.ena(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sclr(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		add_sub_cella_0.cin_used = "true",
		add_sub_cella_0.lut_mask = "69b2",
		add_sub_cella_0.operation_mode = "arithmetic",
		add_sub_cella_0.sum_lutc_input = "cin",
		add_sub_cella_0.lpm_type = "cyclone_lcell";
	cyclone_lcell   add_sub_cella_1
	( 
	.cin(wire_add_sub_cella_0cout[0:0]),
	.combout(wire_add_sub_cella_combout[1:1]),
	.cout(wire_add_sub_cella_1cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[1:1]),
	.datab(wire_add_sub_cella_datab[1:1]),
	.regout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.clk(1'b1),
	.datac(1'b1),
	.datad(1'b1),
	.ena(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sclr(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		add_sub_cella_1.cin_used = "true",
		add_sub_cella_1.lut_mask = "69b2",
		add_sub_cella_1.operation_mode = "arithmetic",
		add_sub_cella_1.sum_lutc_input = "cin",
		add_sub_cella_1.lpm_type = "cyclone_lcell";
	cyclone_lcell   add_sub_cella_2
	( 
	.cin(wire_add_sub_cella_1cout[0:0]),
	.combout(wire_add_sub_cella_combout[2:2]),
	.cout(wire_add_sub_cella_2cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[2:2]),
	.datab(wire_add_sub_cella_datab[2:2]),
	.regout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.clk(1'b1),
	.datac(1'b1),
	.datad(1'b1),
	.ena(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sclr(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		add_sub_cella_2.cin_used = "true",
		add_sub_cella_2.lut_mask = "69b2",
		add_sub_cella_2.operation_mode = "arithmetic",
		add_sub_cella_2.sum_lutc_input = "cin",
		add_sub_cella_2.lpm_type = "cyclone_lcell";
	cyclone_lcell   add_sub_cella_3
	( 
	.cin(wire_add_sub_cella_2cout[0:0]),
	.combout(wire_add_sub_cella_combout[3:3]),
	.cout(wire_add_sub_cella_3cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[3:3]),
	.datab(wire_add_sub_cella_datab[3:3]),
	.regout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.clk(1'b1),
	.datac(1'b1),
	.datad(1'b1),
	.ena(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sclr(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		add_sub_cella_3.cin_used = "true",
		add_sub_cella_3.lut_mask = "69b2",
		add_sub_cella_3.operation_mode = "arithmetic",
		add_sub_cella_3.sum_lutc_input = "cin",
		add_sub_cella_3.lpm_type = "cyclone_lcell";
	cyclone_lcell   add_sub_cella_4
	( 
	.cin(wire_add_sub_cella_3cout[0:0]),
	.combout(wire_add_sub_cella_combout[4:4]),
	.cout(wire_add_sub_cella_4cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[4:4]),
	.datab(wire_add_sub_cella_datab[4:4]),
	.regout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.clk(1'b1),
	.datac(1'b1),
	.datad(1'b1),
	.ena(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sclr(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		add_sub_cella_4.cin_used = "true",
		add_sub_cella_4.lut_mask = "69b2",
		add_sub_cella_4.operation_mode = "arithmetic",
		add_sub_cella_4.sum_lutc_input = "cin",
		add_sub_cella_4.lpm_type = "cyclone_lcell";
	cyclone_lcell   add_sub_cella_5
	( 
	.cin(wire_add_sub_cella_4cout[0:0]),
	.combout(wire_add_sub_cella_combout[5:5]),
	.cout(wire_add_sub_cella_5cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[5:5]),
	.datab(wir