📄 dsptoasi.v
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.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[11:11]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_11portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_11.connectivity_checking = "OFF",
ram_block30a_11.logical_ram_name = "ALTSYNCRAM",
ram_block30a_11.mixed_port_feed_through_mode = "dont_care",
ram_block30a_11.operation_mode = "dual_port",
ram_block30a_11.port_a_address_clear = "none",
ram_block30a_11.port_a_address_width = 8,
ram_block30a_11.port_a_data_in_clear = "none",
ram_block30a_11.port_a_data_width = 1,
ram_block30a_11.port_a_first_address = 0,
ram_block30a_11.port_a_first_bit_number = 11,
ram_block30a_11.port_a_last_address = 255,
ram_block30a_11.port_a_logical_ram_depth = 256,
ram_block30a_11.port_a_logical_ram_width = 16,
ram_block30a_11.port_a_write_enable_clear = "none",
ram_block30a_11.port_b_address_clear = "none",
ram_block30a_11.port_b_address_clock = "clock1",
ram_block30a_11.port_b_address_width = 8,
ram_block30a_11.port_b_data_out_clear = "none",
ram_block30a_11.port_b_data_out_clock = "clock1",
ram_block30a_11.port_b_data_width = 1,
ram_block30a_11.port_b_first_address = 0,
ram_block30a_11.port_b_first_bit_number = 11,
ram_block30a_11.port_b_last_address = 255,
ram_block30a_11.port_b_logical_ram_depth = 256,
ram_block30a_11.port_b_logical_ram_width = 16,
ram_block30a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_11.ram_block_type = "M4K",
ram_block30a_11.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_12
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[12:12]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_12portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_12.connectivity_checking = "OFF",
ram_block30a_12.logical_ram_name = "ALTSYNCRAM",
ram_block30a_12.mixed_port_feed_through_mode = "dont_care",
ram_block30a_12.operation_mode = "dual_port",
ram_block30a_12.port_a_address_clear = "none",
ram_block30a_12.port_a_address_width = 8,
ram_block30a_12.port_a_data_in_clear = "none",
ram_block30a_12.port_a_data_width = 1,
ram_block30a_12.port_a_first_address = 0,
ram_block30a_12.port_a_first_bit_number = 12,
ram_block30a_12.port_a_last_address = 255,
ram_block30a_12.port_a_logical_ram_depth = 256,
ram_block30a_12.port_a_logical_ram_width = 16,
ram_block30a_12.port_a_write_enable_clear = "none",
ram_block30a_12.port_b_address_clear = "none",
ram_block30a_12.port_b_address_clock = "clock1",
ram_block30a_12.port_b_address_width = 8,
ram_block30a_12.port_b_data_out_clear = "none",
ram_block30a_12.port_b_data_out_clock = "clock1",
ram_block30a_12.port_b_data_width = 1,
ram_block30a_12.port_b_first_address = 0,
ram_block30a_12.port_b_first_bit_number = 12,
ram_block30a_12.port_b_last_address = 255,
ram_block30a_12.port_b_logical_ram_depth = 256,
ram_block30a_12.port_b_logical_ram_width = 16,
ram_block30a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_12.ram_block_type = "M4K",
ram_block30a_12.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_13
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[13:13]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_13portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_13.connectivity_checking = "OFF",
ram_block30a_13.logical_ram_name = "ALTSYNCRAM",
ram_block30a_13.mixed_port_feed_through_mode = "dont_care",
ram_block30a_13.operation_mode = "dual_port",
ram_block30a_13.port_a_address_clear = "none",
ram_block30a_13.port_a_address_width = 8,
ram_block30a_13.port_a_data_in_clear = "none",
ram_block30a_13.port_a_data_width = 1,
ram_block30a_13.port_a_first_address = 0,
ram_block30a_13.port_a_first_bit_number = 13,
ram_block30a_13.port_a_last_address = 255,
ram_block30a_13.port_a_logical_ram_depth = 256,
ram_block30a_13.port_a_logical_ram_width = 16,
ram_block30a_13.port_a_write_enable_clear = "none",
ram_block30a_13.port_b_address_clear = "none",
ram_block30a_13.port_b_address_clock = "clock1",
ram_block30a_13.port_b_address_width = 8,
ram_block30a_13.port_b_data_out_clear = "none",
ram_block30a_13.port_b_data_out_clock = "clock1",
ram_block30a_13.port_b_data_width = 1,
ram_block30a_13.port_b_first_address = 0,
ram_block30a_13.port_b_first_bit_number = 13,
ram_block30a_13.port_b_last_address = 255,
ram_block30a_13.port_b_logical_ram_depth = 256,
ram_block30a_13.port_b_logical_ram_width = 16,
ram_block30a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_13.ram_block_type = "M4K",
ram_block30a_13.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_14
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[14:14]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_14portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_14.connectivity_checking = "OFF",
ram_block30a_14.logical_ram_name = "ALTSYNCRAM",
ram_block30a_14.mixed_port_feed_through_mode = "dont_care",
ram_block30a_14.operation_mode = "dual_port",
ram_block30a_14.port_a_address_clear = "none",
ram_block30a_14.port_a_address_width = 8,
ram_block30a_14.port_a_data_in_clear = "none",
ram_block30a_14.port_a_data_width = 1,
ram_block30a_14.port_a_first_address = 0,
ram_block30a_14.port_a_first_bit_number = 14,
ram_block30a_14.port_a_last_address = 255,
ram_block30a_14.port_a_logical_ram_depth = 256,
ram_block30a_14.port_a_logical_ram_width = 16,
ram_block30a_14.port_a_write_enable_clear = "none",
ram_block30a_14.port_b_address_clear = "none",
ram_block30a_14.port_b_address_clock = "clock1",
ram_block30a_14.port_b_address_width = 8,
ram_block30a_14.port_b_data_out_clear = "none",
ram_block30a_14.port_b_data_out_clock = "clock1",
ram_block30a_14.port_b_data_width = 1,
ram_block30a_14.port_b_first_address = 0,
ram_block30a_14.port_b_first_bit_number = 14,
ram_block30a_14.port_b_last_address = 255,
ram_block30a_14.port_b_logical_ram_depth = 256,
ram_block30a_14.port_b_logical_ram_width = 16,
ram_block30a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_14.ram_block_type = "M4K",
ram_block30a_14.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_15
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[15:15]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_15portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_15.connectivity_checking = "OFF",
ram_block30a_15.logical_ram_name = "ALTSYNCRAM",
ram_block30a_15.mixed_port_feed_through_mode = "dont_care",
ram_block30a_15.operation_mode = "dual_port",
ram_block30a_15.port_a_address_clear = "none",
ram_block30a_15.port_a_address_width = 8,
ram_block30a_15.port_a_data_in_clear = "none",
ram_block30a_15.port_a_data_width = 1,
ram_block30a_15.port_a_first_address = 0,
ram_block30a_15.port_a_first_bit_number = 15,
ram_block30a_15.port_a_last_address = 255,
ram_block30a_15.port_a_logical_ram_depth = 256,
ram_block30a_15.port_a_logical_ram_width = 16,
ram_block30a_15.port_a_write_enable_clear = "none",
ram_block30a_15.port_b_address_clear = "none",
ram_block30a_15.port_b_address_clock = "clock1",
ram_block30a_15.port_b_address_width = 8,
ram_block30a_15.port_b_data_out_clear = "none",
ram_block30a_15.port_b_data_out_clock = "clock1",
ram_block30a_15.port_b_data_width = 1,
ram_block30a_15.port_b_first_address = 0,
ram_block30a_15.port_b_first_bit_number = 15,
ram_block30a_15.port_b_last_address = 255,
ram_block30a_15.port_b_logical_ram_depth = 256,
ram_block30a_15.port_b_logical_ram_width = 16,
ram_block30a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_15.ram_block_type = "M4K",
ram_block30a_15.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block30a_15portbdataout[0:0], wire_ram_block30a_14portbdataout[0:0], wire_ram_block30a_13portbdataout[0:0], wire_ram_block30a_12portbdataout[0:0], wire_ram_block30a_11portbdataout[0:0], wire_ram_block30a_10portbdataout[0:0], wire_ram_block30a_9portbdataout[0:0], wire_ram_block30a_8portbdataout[0:0], wire_ram_block30a_7portbdataout[0:0], wire_ram_block30a_6portbdataout[0:0], wire_ram_block30a_5portbdataout[0:0], wire_ram_block30a_4portbdataout[0:0], wire_ram_block30a_3portbdataout[0:0], wire_ram_block30a_2portbdataout[0:0], wire_ram_block30a_1portbdataout[0:0], wire_ram_block30a_0portbdataout[0:0]};
endmodule //dsptoasi_altsyncram_bv01
//dffpipe DELAY=3 WIDTH=8 clock clrn d q
//VERSION_BEGIN 4.1 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:03:05:02:46:42:SJ cbx_altdpram 2004:05:14:13:10:08:SJ cbx_altsyncram 2004:06:23:18:19:30:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_dcfifo 2004:06:03:11:08:42:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 2004:04:12:17:30:12:SJ cbx_lpm_counter 2004:04:21:01:21:20:SJ cbx_lpm_decode 2004:03:10:10:44:06:SJ cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_scfifo 2004:06:03:11:12:32:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ VERSION_END
//dffpipe DELAY=3 WIDTH=8 clock clrn d q
//VERSION_BEGIN 4.1 cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ VERSION_END
//synthesis_resources = lut 24
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module dsptoasi_dffpipe_2a3
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [7:0] d;
output [7:0] q;
wire [7:0] wire_dffe32a_D;
reg [7:0] dffe32a;
wire [7:0] wire_dffe33a_D;
reg [7:0] dffe33a;
wire [7:0] wire_dffe34a_D;
reg [7:0] dffe34a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe32a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe32a[0:0] <= 1;
else if (clrn == 1'b0) dffe32a[0:0] <= 0;
else if (ena == 1'b1) dffe32a[0:0] <= wire_dffe32a_D[0:0];
// synopsys translate_off
initial
dffe32a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe32a[1:1] <= 1;
else if (clrn == 1'b0) dffe32a[1:1] <= 0;
else if (ena == 1'b1) dffe32a[1:1] <= wire_dffe32a_D[1:1];
// synopsys translate_off
initial
dffe32a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe32a[2:2] <= 1;
else if (clrn == 1'b0) dffe32a[2:2] <= 0;
else if (ena == 1'b1) dffe32a[2:2] <= wire_dffe32a_D[2:2];
// synopsys translate_off
initial
dffe32a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe32a[3:3] <= 1;
else if (clrn == 1'b0) dffe32a[3:3] <= 0;
else if (ena == 1'b1) dffe32a[3:3] <= wire_dffe32a_D[3:3];
// synopsys translate_off
initial
dffe32a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe32a[4:4] <= 1;
else if (clrn == 1'b0) dffe32a[4:4] <= 0;
else if (ena == 1'b1) dffe32a[4:4] <= wire_dffe32a_D[4:4];
// synopsys translate_off
initial
dffe32a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe32a[5:5] <= 1;
else if (clrn == 1'b0) dffe32a[5:5] <= 0;
else if (ena == 1'b1) dffe32a[5:5] <= wire_dffe32a_D[5:5];
// synopsys translate_off
initial
dffe32a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe32a[6:6] <= 1;
else if (clrn == 1'b0) dffe32a[6:6] <= 0;
else if (ena == 1'b1) dffe32a[6:6] <= wire_dffe32a_D[6:6];
// synopsys translate_off
initial
dffe32a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe32a[7:7] <= 1;
else if (clrn == 1'b0) dffe32a[7:7] <= 0;
else if (ena == 1'b1) dffe32a[7:7] <= wire_dffe32a_D[7:7];
assign
wire_dffe32a_D = (d & {8{(~ sclr)}});
// synopsys translate_off
initial
dffe33a[0:0] = 0;
// synopsys translate_on
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