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`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_4.connectivity_checking = "OFF",
ram_block30a_4.logical_ram_name = "ALTSYNCRAM",
ram_block30a_4.mixed_port_feed_through_mode = "dont_care",
ram_block30a_4.operation_mode = "dual_port",
ram_block30a_4.port_a_address_clear = "none",
ram_block30a_4.port_a_address_width = 8,
ram_block30a_4.port_a_data_in_clear = "none",
ram_block30a_4.port_a_data_width = 1,
ram_block30a_4.port_a_first_address = 0,
ram_block30a_4.port_a_first_bit_number = 4,
ram_block30a_4.port_a_last_address = 255,
ram_block30a_4.port_a_logical_ram_depth = 256,
ram_block30a_4.port_a_logical_ram_width = 16,
ram_block30a_4.port_a_write_enable_clear = "none",
ram_block30a_4.port_b_address_clear = "none",
ram_block30a_4.port_b_address_clock = "clock1",
ram_block30a_4.port_b_address_width = 8,
ram_block30a_4.port_b_data_out_clear = "none",
ram_block30a_4.port_b_data_out_clock = "clock1",
ram_block30a_4.port_b_data_width = 1,
ram_block30a_4.port_b_first_address = 0,
ram_block30a_4.port_b_first_bit_number = 4,
ram_block30a_4.port_b_last_address = 255,
ram_block30a_4.port_b_logical_ram_depth = 256,
ram_block30a_4.port_b_logical_ram_width = 16,
ram_block30a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_4.ram_block_type = "M4K",
ram_block30a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_5
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[5:5]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_5portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_5.connectivity_checking = "OFF",
ram_block30a_5.logical_ram_name = "ALTSYNCRAM",
ram_block30a_5.mixed_port_feed_through_mode = "dont_care",
ram_block30a_5.operation_mode = "dual_port",
ram_block30a_5.port_a_address_clear = "none",
ram_block30a_5.port_a_address_width = 8,
ram_block30a_5.port_a_data_in_clear = "none",
ram_block30a_5.port_a_data_width = 1,
ram_block30a_5.port_a_first_address = 0,
ram_block30a_5.port_a_first_bit_number = 5,
ram_block30a_5.port_a_last_address = 255,
ram_block30a_5.port_a_logical_ram_depth = 256,
ram_block30a_5.port_a_logical_ram_width = 16,
ram_block30a_5.port_a_write_enable_clear = "none",
ram_block30a_5.port_b_address_clear = "none",
ram_block30a_5.port_b_address_clock = "clock1",
ram_block30a_5.port_b_address_width = 8,
ram_block30a_5.port_b_data_out_clear = "none",
ram_block30a_5.port_b_data_out_clock = "clock1",
ram_block30a_5.port_b_data_width = 1,
ram_block30a_5.port_b_first_address = 0,
ram_block30a_5.port_b_first_bit_number = 5,
ram_block30a_5.port_b_last_address = 255,
ram_block30a_5.port_b_logical_ram_depth = 256,
ram_block30a_5.port_b_logical_ram_width = 16,
ram_block30a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_5.ram_block_type = "M4K",
ram_block30a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_6
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[6:6]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_6portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_6.connectivity_checking = "OFF",
ram_block30a_6.logical_ram_name = "ALTSYNCRAM",
ram_block30a_6.mixed_port_feed_through_mode = "dont_care",
ram_block30a_6.operation_mode = "dual_port",
ram_block30a_6.port_a_address_clear = "none",
ram_block30a_6.port_a_address_width = 8,
ram_block30a_6.port_a_data_in_clear = "none",
ram_block30a_6.port_a_data_width = 1,
ram_block30a_6.port_a_first_address = 0,
ram_block30a_6.port_a_first_bit_number = 6,
ram_block30a_6.port_a_last_address = 255,
ram_block30a_6.port_a_logical_ram_depth = 256,
ram_block30a_6.port_a_logical_ram_width = 16,
ram_block30a_6.port_a_write_enable_clear = "none",
ram_block30a_6.port_b_address_clear = "none",
ram_block30a_6.port_b_address_clock = "clock1",
ram_block30a_6.port_b_address_width = 8,
ram_block30a_6.port_b_data_out_clear = "none",
ram_block30a_6.port_b_data_out_clock = "clock1",
ram_block30a_6.port_b_data_width = 1,
ram_block30a_6.port_b_first_address = 0,
ram_block30a_6.port_b_first_bit_number = 6,
ram_block30a_6.port_b_last_address = 255,
ram_block30a_6.port_b_logical_ram_depth = 256,
ram_block30a_6.port_b_logical_ram_width = 16,
ram_block30a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_6.ram_block_type = "M4K",
ram_block30a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_7
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[7:7]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_7portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_7.connectivity_checking = "OFF",
ram_block30a_7.logical_ram_name = "ALTSYNCRAM",
ram_block30a_7.mixed_port_feed_through_mode = "dont_care",
ram_block30a_7.operation_mode = "dual_port",
ram_block30a_7.port_a_address_clear = "none",
ram_block30a_7.port_a_address_width = 8,
ram_block30a_7.port_a_data_in_clear = "none",
ram_block30a_7.port_a_data_width = 1,
ram_block30a_7.port_a_first_address = 0,
ram_block30a_7.port_a_first_bit_number = 7,
ram_block30a_7.port_a_last_address = 255,
ram_block30a_7.port_a_logical_ram_depth = 256,
ram_block30a_7.port_a_logical_ram_width = 16,
ram_block30a_7.port_a_write_enable_clear = "none",
ram_block30a_7.port_b_address_clear = "none",
ram_block30a_7.port_b_address_clock = "clock1",
ram_block30a_7.port_b_address_width = 8,
ram_block30a_7.port_b_data_out_clear = "none",
ram_block30a_7.port_b_data_out_clock = "clock1",
ram_block30a_7.port_b_data_width = 1,
ram_block30a_7.port_b_first_address = 0,
ram_block30a_7.port_b_first_bit_number = 7,
ram_block30a_7.port_b_last_address = 255,
ram_block30a_7.port_b_logical_ram_depth = 256,
ram_block30a_7.port_b_logical_ram_width = 16,
ram_block30a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_7.ram_block_type = "M4K",
ram_block30a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_8
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[8:8]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_8portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_8.connectivity_checking = "OFF",
ram_block30a_8.logical_ram_name = "ALTSYNCRAM",
ram_block30a_8.mixed_port_feed_through_mode = "dont_care",
ram_block30a_8.operation_mode = "dual_port",
ram_block30a_8.port_a_address_clear = "none",
ram_block30a_8.port_a_address_width = 8,
ram_block30a_8.port_a_data_in_clear = "none",
ram_block30a_8.port_a_data_width = 1,
ram_block30a_8.port_a_first_address = 0,
ram_block30a_8.port_a_first_bit_number = 8,
ram_block30a_8.port_a_last_address = 255,
ram_block30a_8.port_a_logical_ram_depth = 256,
ram_block30a_8.port_a_logical_ram_width = 16,
ram_block30a_8.port_a_write_enable_clear = "none",
ram_block30a_8.port_b_address_clear = "none",
ram_block30a_8.port_b_address_clock = "clock1",
ram_block30a_8.port_b_address_width = 8,
ram_block30a_8.port_b_data_out_clear = "none",
ram_block30a_8.port_b_data_out_clock = "clock1",
ram_block30a_8.port_b_data_width = 1,
ram_block30a_8.port_b_first_address = 0,
ram_block30a_8.port_b_first_bit_number = 8,
ram_block30a_8.port_b_last_address = 255,
ram_block30a_8.port_b_logical_ram_depth = 256,
ram_block30a_8.port_b_logical_ram_width = 16,
ram_block30a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_8.ram_block_type = "M4K",
ram_block30a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_9
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[9:9]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_9portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_9.connectivity_checking = "OFF",
ram_block30a_9.logical_ram_name = "ALTSYNCRAM",
ram_block30a_9.mixed_port_feed_through_mode = "dont_care",
ram_block30a_9.operation_mode = "dual_port",
ram_block30a_9.port_a_address_clear = "none",
ram_block30a_9.port_a_address_width = 8,
ram_block30a_9.port_a_data_in_clear = "none",
ram_block30a_9.port_a_data_width = 1,
ram_block30a_9.port_a_first_address = 0,
ram_block30a_9.port_a_first_bit_number = 9,
ram_block30a_9.port_a_last_address = 255,
ram_block30a_9.port_a_logical_ram_depth = 256,
ram_block30a_9.port_a_logical_ram_width = 16,
ram_block30a_9.port_a_write_enable_clear = "none",
ram_block30a_9.port_b_address_clear = "none",
ram_block30a_9.port_b_address_clock = "clock1",
ram_block30a_9.port_b_address_width = 8,
ram_block30a_9.port_b_data_out_clear = "none",
ram_block30a_9.port_b_data_out_clock = "clock1",
ram_block30a_9.port_b_data_width = 1,
ram_block30a_9.port_b_first_address = 0,
ram_block30a_9.port_b_first_bit_number = 9,
ram_block30a_9.port_b_last_address = 255,
ram_block30a_9.port_b_logical_ram_depth = 256,
ram_block30a_9.port_b_logical_ram_width = 16,
ram_block30a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_9.ram_block_type = "M4K",
ram_block30a_9.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_10
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
.portadatain({{143{1'b0}}, data_a[10:10]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
.portbdataout(wire_ram_block30a_10portbdataout[143:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.portabyteenamasks(16'b1111111111111111),
.portbbyteenamasks(16'b1111111111111111),
.portbdatain(72'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block30a_10.connectivity_checking = "OFF",
ram_block30a_10.logical_ram_name = "ALTSYNCRAM",
ram_block30a_10.mixed_port_feed_through_mode = "dont_care",
ram_block30a_10.operation_mode = "dual_port",
ram_block30a_10.port_a_address_clear = "none",
ram_block30a_10.port_a_address_width = 8,
ram_block30a_10.port_a_data_in_clear = "none",
ram_block30a_10.port_a_data_width = 1,
ram_block30a_10.port_a_first_address = 0,
ram_block30a_10.port_a_first_bit_number = 10,
ram_block30a_10.port_a_last_address = 255,
ram_block30a_10.port_a_logical_ram_depth = 256,
ram_block30a_10.port_a_logical_ram_width = 16,
ram_block30a_10.port_a_write_enable_clear = "none",
ram_block30a_10.port_b_address_clear = "none",
ram_block30a_10.port_b_address_clock = "clock1",
ram_block30a_10.port_b_address_width = 8,
ram_block30a_10.port_b_data_out_clear = "none",
ram_block30a_10.port_b_data_out_clock = "clock1",
ram_block30a_10.port_b_data_width = 1,
ram_block30a_10.port_b_first_address = 0,
ram_block30a_10.port_b_first_bit_number = 10,
ram_block30a_10.port_b_last_address = 255,
ram_block30a_10.port_b_logical_ram_depth = 256,
ram_block30a_10.port_b_logical_ram_width = 16,
ram_block30a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block30a_10.ram_block_type = "M4K",
ram_block30a_10.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block30a_11
(
.clk0(clock0),
.clk1(clock1),
.ena1(clocken1),
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