dsptoasi.v

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

		countera_6.synch_mode = "on",
		countera_6.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_7
	( 
	.aclr(aclr),
	.cin(wire_countera_6cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(),
	.dataa(power_modified_counter_values[7:7]),
	.ena(clk_en),
	.regout(wire_countera_regout[7:7]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datab(1'b1),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_7.cin_used = "true",
		countera_7.lut_mask = "5a5a",
		countera_7.operation_mode = "normal",
		countera_7.sum_lutc_input = "cin",
		countera_7.synch_mode = "on",
		countera_7.lpm_type = "cyclone_lcell";
	cyclone_lcell   parity
	( 
	.aclr(aclr),
	.cin(updown),
	.clk(clock),
	.combout(),
	.cout(wire_parity_cout),
	.dataa(cnt_en),
	.datab(wire_parity_regout),
	.ena(clk_en),
	.regout(wire_parity_regout),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		parity.cin_used = "true",
		parity.lut_mask = "6682",
		parity.operation_mode = "arithmetic",
		parity.synch_mode = "on",
		parity.lpm_type = "cyclone_lcell";
	assign
		cnt_en = 1'b1,
		power_modified_counter_values = {wire_countera_regout[7:0]},
		q = power_modified_counter_values,
		sclr = 1'b0,
		updown = 1'b1;
endmodule //dsptoasi_a_graycounter_i06


//altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="NONE" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="M4K" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 WIDTHAD_B=8 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
//VERSION_BEGIN 4.1 cbx_altsyncram 2004:06:23:18:19:30:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 2004:04:12:17:30:12:SJ cbx_lpm_decode 2004:03:10:10:44:06:SJ cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ  VERSION_END

//synthesis_resources = ram_bits (M4K) 4096 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  dsptoasi_altsyncram_bv01
	( 
	address_a,
	address_b,
	clock0,
	clock1,
	clocken1,
	data_a,
	q_b,
	wren_a) /* synthesis synthesis_clearbox=1 */;
	input   [7:0]  address_a;
	input   [7:0]  address_b;
	input   clock0;
	input   clock1;
	input   clocken1;
	input   [15:0]  data_a;
	output   [15:0]  q_b;
	input   wren_a;

	wire  [143:0]   wire_ram_block30a_0portbdataout;
	wire  [143:0]   wire_ram_block30a_1portbdataout;
	wire  [143:0]   wire_ram_block30a_2portbdataout;
	wire  [143:0]   wire_ram_block30a_3portbdataout;
	wire  [143:0]   wire_ram_block30a_4portbdataout;
	wire  [143:0]   wire_ram_block30a_5portbdataout;
	wire  [143:0]   wire_ram_block30a_6portbdataout;
	wire  [143:0]   wire_ram_block30a_7portbdataout;
	wire  [143:0]   wire_ram_block30a_8portbdataout;
	wire  [143:0]   wire_ram_block30a_9portbdataout;
	wire  [143:0]   wire_ram_block30a_10portbdataout;
	wire  [143:0]   wire_ram_block30a_11portbdataout;
	wire  [143:0]   wire_ram_block30a_12portbdataout;
	wire  [143:0]   wire_ram_block30a_13portbdataout;
	wire  [143:0]   wire_ram_block30a_14portbdataout;
	wire  [143:0]   wire_ram_block30a_15portbdataout;
	wire  [7:0]  address_a_wire;
	wire  [7:0]  address_b_wire;

	cyclone_ram_block   ram_block30a_0
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena1(clocken1),
	.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
	.portadatain({{143{1'b0}}, data_a[0:0]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
	.portbdataout(wire_ram_block30a_0portbdataout[143:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.portabyteenamasks(16'b1111111111111111),
	.portbbyteenamasks(16'b1111111111111111),
	.portbdatain(72'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block30a_0.connectivity_checking = "OFF",
		ram_block30a_0.logical_ram_name = "ALTSYNCRAM",
		ram_block30a_0.mixed_port_feed_through_mode = "dont_care",
		ram_block30a_0.operation_mode = "dual_port",
		ram_block30a_0.port_a_address_clear = "none",
		ram_block30a_0.port_a_address_width = 8,
		ram_block30a_0.port_a_data_in_clear = "none",
		ram_block30a_0.port_a_data_width = 1,
		ram_block30a_0.port_a_first_address = 0,
		ram_block30a_0.port_a_first_bit_number = 0,
		ram_block30a_0.port_a_last_address = 255,
		ram_block30a_0.port_a_logical_ram_depth = 256,
		ram_block30a_0.port_a_logical_ram_width = 16,
		ram_block30a_0.port_a_write_enable_clear = "none",
		ram_block30a_0.port_b_address_clear = "none",
		ram_block30a_0.port_b_address_clock = "clock1",
		ram_block30a_0.port_b_address_width = 8,
		ram_block30a_0.port_b_data_out_clear = "none",
		ram_block30a_0.port_b_data_out_clock = "clock1",
		ram_block30a_0.port_b_data_width = 1,
		ram_block30a_0.port_b_first_address = 0,
		ram_block30a_0.port_b_first_bit_number = 0,
		ram_block30a_0.port_b_last_address = 255,
		ram_block30a_0.port_b_logical_ram_depth = 256,
		ram_block30a_0.port_b_logical_ram_width = 16,
		ram_block30a_0.port_b_read_enable_write_enable_clock = "clock1",
		ram_block30a_0.ram_block_type = "M4K",
		ram_block30a_0.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block30a_1
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena1(clocken1),
	.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
	.portadatain({{143{1'b0}}, data_a[1:1]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
	.portbdataout(wire_ram_block30a_1portbdataout[143:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.portabyteenamasks(16'b1111111111111111),
	.portbbyteenamasks(16'b1111111111111111),
	.portbdatain(72'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block30a_1.connectivity_checking = "OFF",
		ram_block30a_1.logical_ram_name = "ALTSYNCRAM",
		ram_block30a_1.mixed_port_feed_through_mode = "dont_care",
		ram_block30a_1.operation_mode = "dual_port",
		ram_block30a_1.port_a_address_clear = "none",
		ram_block30a_1.port_a_address_width = 8,
		ram_block30a_1.port_a_data_in_clear = "none",
		ram_block30a_1.port_a_data_width = 1,
		ram_block30a_1.port_a_first_address = 0,
		ram_block30a_1.port_a_first_bit_number = 1,
		ram_block30a_1.port_a_last_address = 255,
		ram_block30a_1.port_a_logical_ram_depth = 256,
		ram_block30a_1.port_a_logical_ram_width = 16,
		ram_block30a_1.port_a_write_enable_clear = "none",
		ram_block30a_1.port_b_address_clear = "none",
		ram_block30a_1.port_b_address_clock = "clock1",
		ram_block30a_1.port_b_address_width = 8,
		ram_block30a_1.port_b_data_out_clear = "none",
		ram_block30a_1.port_b_data_out_clock = "clock1",
		ram_block30a_1.port_b_data_width = 1,
		ram_block30a_1.port_b_first_address = 0,
		ram_block30a_1.port_b_first_bit_number = 1,
		ram_block30a_1.port_b_last_address = 255,
		ram_block30a_1.port_b_logical_ram_depth = 256,
		ram_block30a_1.port_b_logical_ram_width = 16,
		ram_block30a_1.port_b_read_enable_write_enable_clock = "clock1",
		ram_block30a_1.ram_block_type = "M4K",
		ram_block30a_1.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block30a_2
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena1(clocken1),
	.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
	.portadatain({{143{1'b0}}, data_a[2:2]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
	.portbdataout(wire_ram_block30a_2portbdataout[143:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.portabyteenamasks(16'b1111111111111111),
	.portbbyteenamasks(16'b1111111111111111),
	.portbdatain(72'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block30a_2.connectivity_checking = "OFF",
		ram_block30a_2.logical_ram_name = "ALTSYNCRAM",
		ram_block30a_2.mixed_port_feed_through_mode = "dont_care",
		ram_block30a_2.operation_mode = "dual_port",
		ram_block30a_2.port_a_address_clear = "none",
		ram_block30a_2.port_a_address_width = 8,
		ram_block30a_2.port_a_data_in_clear = "none",
		ram_block30a_2.port_a_data_width = 1,
		ram_block30a_2.port_a_first_address = 0,
		ram_block30a_2.port_a_first_bit_number = 2,
		ram_block30a_2.port_a_last_address = 255,
		ram_block30a_2.port_a_logical_ram_depth = 256,
		ram_block30a_2.port_a_logical_ram_width = 16,
		ram_block30a_2.port_a_write_enable_clear = "none",
		ram_block30a_2.port_b_address_clear = "none",
		ram_block30a_2.port_b_address_clock = "clock1",
		ram_block30a_2.port_b_address_width = 8,
		ram_block30a_2.port_b_data_out_clear = "none",
		ram_block30a_2.port_b_data_out_clock = "clock1",
		ram_block30a_2.port_b_data_width = 1,
		ram_block30a_2.port_b_first_address = 0,
		ram_block30a_2.port_b_first_bit_number = 2,
		ram_block30a_2.port_b_last_address = 255,
		ram_block30a_2.port_b_logical_ram_depth = 256,
		ram_block30a_2.port_b_logical_ram_width = 16,
		ram_block30a_2.port_b_read_enable_write_enable_clock = "clock1",
		ram_block30a_2.ram_block_type = "M4K",
		ram_block30a_2.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block30a_3
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena1(clocken1),
	.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
	.portadatain({{143{1'b0}}, data_a[3:3]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
	.portbdataout(wire_ram_block30a_3portbdataout[143:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.portabyteenamasks(16'b1111111111111111),
	.portbbyteenamasks(16'b1111111111111111),
	.portbdatain(72'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		ram_block30a_3.connectivity_checking = "OFF",
		ram_block30a_3.logical_ram_name = "ALTSYNCRAM",
		ram_block30a_3.mixed_port_feed_through_mode = "dont_care",
		ram_block30a_3.operation_mode = "dual_port",
		ram_block30a_3.port_a_address_clear = "none",
		ram_block30a_3.port_a_address_width = 8,
		ram_block30a_3.port_a_data_in_clear = "none",
		ram_block30a_3.port_a_data_width = 1,
		ram_block30a_3.port_a_first_address = 0,
		ram_block30a_3.port_a_first_bit_number = 3,
		ram_block30a_3.port_a_last_address = 255,
		ram_block30a_3.port_a_logical_ram_depth = 256,
		ram_block30a_3.port_a_logical_ram_width = 16,
		ram_block30a_3.port_a_write_enable_clear = "none",
		ram_block30a_3.port_b_address_clear = "none",
		ram_block30a_3.port_b_address_clock = "clock1",
		ram_block30a_3.port_b_address_width = 8,
		ram_block30a_3.port_b_data_out_clear = "none",
		ram_block30a_3.port_b_data_out_clock = "clock1",
		ram_block30a_3.port_b_data_width = 1,
		ram_block30a_3.port_b_first_address = 0,
		ram_block30a_3.port_b_first_bit_number = 3,
		ram_block30a_3.port_b_last_address = 255,
		ram_block30a_3.port_b_logical_ram_depth = 256,
		ram_block30a_3.port_b_logical_ram_width = 16,
		ram_block30a_3.port_b_read_enable_write_enable_clock = "clock1",
		ram_block30a_3.ram_block_type = "M4K",
		ram_block30a_3.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block30a_4
	( 
	.clk0(clock0),
	.clk1(clock1),
	.ena1(clocken1),
	.portaaddr({{8{1'b0}}, address_a_wire[7:0]}),
	.portadatain({{143{1'b0}}, data_a[4:4]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({{8{1'b0}}, address_b_wire[7:0]}),
	.portbdataout(wire_ram_block30a_4portbdataout[143:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.portabyteenamasks(16'b1111111111111111),
	.portbbyteenamasks(16'b1111111111111111),
	.portbdatain(72'b0)
	`ifdef FORMAL_VERIFICATION