dsptoasi.v

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

// megafunction wizard: %LPM_FIFO+%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo 

// ============================================================
// File Name: dsptoasi.v
// Megafunction Name(s):
// 			dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.1 Build 181 06/29/2004 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2004 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
//any other  silicon devices,  unless such use is  explicitly  licensed under
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//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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//licensors. No other licenses, including any licenses needed under any third
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//dcfifo ADD_RAM_OUTPUT_REGISTER="ON" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=256 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=8 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdreq wrclk wrreq lpm_hint="RAM_BLOCK_TYPE=M4K" RAM_BLOCK_TYPE="M4K"
//VERSION_BEGIN 4.1 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:03:05:02:46:42:SJ cbx_altdpram 2004:05:14:13:10:08:SJ cbx_altsyncram 2004:06:23:18:19:30:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_dcfifo 2004:06:03:11:08:42:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 2004:04:12:17:30:12:SJ cbx_lpm_counter 2004:04:21:01:21:20:SJ cbx_lpm_decode 2004:03:10:10:44:06:SJ cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_scfifo 2004:06:03:11:12:32:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ  VERSION_END


//a_gray2bin device_family="Cyclone" WIDTH=8 bin gray
//VERSION_BEGIN 4.1 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ  VERSION_END

//synthesis_resources = 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  dsptoasi_a_gray2bin_uk4
	( 
	bin,
	gray) /* synthesis synthesis_clearbox=1 */;
	output   [7:0]  bin;
	input   [7:0]  gray;

	wire  xor0;
	wire  xor1;
	wire  xor2;
	wire  xor3;
	wire  xor4;
	wire  xor5;
	wire  xor6;

	assign
		bin = {gray[7:7], xor6, xor5, xor4, xor3, xor2, xor1, xor0},
		xor0 = (gray[0:0] ^ xor1),
		xor1 = (gray[1:1] ^ xor2),
		xor2 = (gray[2:2] ^ xor3),
		xor3 = (gray[3:3] ^ xor4),
		xor4 = (gray[4:4] ^ xor5),
		xor5 = (gray[5:5] ^ xor6),
		xor6 = (gray[7:7] ^ gray[6:6]);
endmodule //dsptoasi_a_gray2bin_uk4


//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=8 aclr clk_en clock q
//VERSION_BEGIN 4.1 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:03:05:02:46:42:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ  VERSION_END

//synthesis_resources = lut 9 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  dsptoasi_a_graycounter_i06
	( 
	aclr,
	clk_en,
	clock,
	q) /* synthesis synthesis_clearbox=1 */;
	input   aclr;
	input   clk_en;
	input   clock;
	output   [7:0]  q;

	wire  [0:0]   wire_countera_0cout;
	wire  [0:0]   wire_countera_1cout;
	wire  [0:0]   wire_countera_2cout;
	wire  [0:0]   wire_countera_3cout;
	wire  [0:0]   wire_countera_4cout;
	wire  [0:0]   wire_countera_5cout;
	wire  [0:0]   wire_countera_6cout;
	wire  [7:0]   wire_countera_regout;
	wire  wire_parity_cout;
	wire  wire_parity_regout;
	wire cnt_en;
	wire  [7:0]  power_modified_counter_values;
	wire sclr;
	wire updown;

	cyclone_lcell   countera_0
	( 
	.aclr(aclr),
	.cin(wire_parity_cout),
	.clk(clock),
	.combout(),
	.cout(wire_countera_0cout[0:0]),
	.dataa(cnt_en),
	.datab(wire_countera_regout[0:0]),
	.ena(clk_en),
	.regout(wire_countera_regout[0:0]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_0.cin_used = "true",
		countera_0.lut_mask = "c6a0",
		countera_0.operation_mode = "arithmetic",
		countera_0.sum_lutc_input = "cin",
		countera_0.synch_mode = "on",
		countera_0.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_1
	( 
	.aclr(aclr),
	.cin(wire_countera_0cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_1cout[0:0]),
	.dataa(power_modified_counter_values[0:0]),
	.datab(power_modified_counter_values[1:1]),
	.ena(clk_en),
	.regout(wire_countera_regout[1:1]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_1.cin_used = "true",
		countera_1.lut_mask = "6c50",
		countera_1.operation_mode = "arithmetic",
		countera_1.sum_lutc_input = "cin",
		countera_1.synch_mode = "on",
		countera_1.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_2
	( 
	.aclr(aclr),
	.cin(wire_countera_1cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_2cout[0:0]),
	.dataa(power_modified_counter_values[1:1]),
	.datab(power_modified_counter_values[2:2]),
	.ena(clk_en),
	.regout(wire_countera_regout[2:2]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_2.cin_used = "true",
		countera_2.lut_mask = "6c50",
		countera_2.operation_mode = "arithmetic",
		countera_2.sum_lutc_input = "cin",
		countera_2.synch_mode = "on",
		countera_2.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_3
	( 
	.aclr(aclr),
	.cin(wire_countera_2cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_3cout[0:0]),
	.dataa(power_modified_counter_values[2:2]),
	.datab(power_modified_counter_values[3:3]),
	.ena(clk_en),
	.regout(wire_countera_regout[3:3]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_3.cin_used = "true",
		countera_3.lut_mask = "6c50",
		countera_3.operation_mode = "arithmetic",
		countera_3.sum_lutc_input = "cin",
		countera_3.synch_mode = "on",
		countera_3.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_4
	( 
	.aclr(aclr),
	.cin(wire_countera_3cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_4cout[0:0]),
	.dataa(power_modified_counter_values[3:3]),
	.datab(power_modified_counter_values[4:4]),
	.ena(clk_en),
	.regout(wire_countera_regout[4:4]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_4.cin_used = "true",
		countera_4.lut_mask = "6c50",
		countera_4.operation_mode = "arithmetic",
		countera_4.sum_lutc_input = "cin",
		countera_4.synch_mode = "on",
		countera_4.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_5
	( 
	.aclr(aclr),
	.cin(wire_countera_4cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_5cout[0:0]),
	.dataa(power_modified_counter_values[4:4]),
	.datab(power_modified_counter_values[5:5]),
	.ena(clk_en),
	.regout(wire_countera_regout[5:5]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_5.cin_used = "true",
		countera_5.lut_mask = "6c50",
		countera_5.operation_mode = "arithmetic",
		countera_5.sum_lutc_input = "cin",
		countera_5.synch_mode = "on",
		countera_5.lpm_type = "cyclone_lcell";
	cyclone_lcell   countera_6
	( 
	.aclr(aclr),
	.cin(wire_countera_5cout[0:0]),
	.clk(clock),
	.combout(),
	.cout(wire_countera_6cout[0:0]),
	.dataa(power_modified_counter_values[5:5]),
	.datab(power_modified_counter_values[6:6]),
	.ena(clk_en),
	.regout(wire_countera_regout[6:6]),
	.sclr(sclr)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.datac(1'b1),
	.datad(1'b1),
	.inverta(1'b0),
	.regcascin(1'b0),
	.sload(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.cin0(),
	.cin1(),
	.cout0(),
	.cout1(),
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		countera_6.cin_used = "true",
		countera_6.lut_mask = "6c50",
		countera_6.operation_mode = "arithmetic",
		countera_6.sum_lutc_input = "cin",