selecet_device.v

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
// Created on Mon Aug 30 09:49:33 2004

//  Module Declaration
module selecet_device
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	data, ain, outb
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [15:0] data;
	input  ain;
	output [7:0] outb;
	reg [7:0] outb;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

always @(ain or data[15:0])
begin
case (ain)

1'b1:
   begin
   outb[7]=data[15]; outb[6]=data[14]; outb[5]=data[13]; outb[4]=data[12];
  outb[3]=data[11]; outb[2]=data[10]; outb[1]=data[9]; outb[0]=data[8];
  end
1'b0:
 begin
   outb[7]=data[7]; outb[6]=data[6]; outb[5]=data[5]; outb[4]=data[4];
   outb[3]=data[3]; outb[2]=data[2]; outb[1]=data[1]; outb[0]=data[0];
  end
default:
   begin
  outb=8'h11;
  end

 endcase
end

endmodule