fifoasi.tan.qmsg

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

{ "Info" "ITDB_FULL_SLACK_RESULT" "ASICLK register 16to8ddf:inst21\|lpm_dff4:inst\|lpm_ff:lpm_ff_component\|dffs\[3\] pin TXDA\[3\] 4.281 ns " "Info: Slack time is 4.281 ns for clock ASICLK between source register 16to8ddf:inst21\|lpm_dff4:inst\|lpm_ff:lpm_ff_component\|dffs\[3\] and destination pin TXDA\[3\]" { { "Info" "ITDB_FULL_TCO_REQUIREMENT" "15.000 ns + register " "Info: + tco requirement for source register and destination pin is 15.000 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TCO_RESULT" "10.719 ns - " "Info: - tco from clock to output pin is 10.719 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "ASICLK altpll0:inst17\|altpll:altpll_component\|_clk0 -1.443 ns + " "Info: + Offset between input clock ASICLK and output clock altpll0:inst17\|altpll:altpll_component\|_clk0 is -1.443 ns" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 1648 16 184 1664 "ASICLK" "" } } } } { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 699 3 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst17\|altpll:altpll_component\|_clk0 source 6.405 ns + Longest register " "Info: + Longest clock path from clock altpll0:inst17\|altpll:altpll_component\|_clk0 to source register is 6.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst17\|altpll:altpll_component\|_clk0 1 CLK PLL_2 69 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 69; CLK Node = 'altpll0:inst17\|altpll:altpll_component\|_clk0'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { altpll0:inst17|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 699 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.576 ns) + CELL(0.935 ns) 2.511 ns 16to8ddf:inst21\|lpm_tff1:inst5\|lpm_ff:lpm_ff_component\|dffs\[0\] 2 REG LC_X8_Y8_N5 581 " "Info: 2: + IC(1.576 ns) + CELL(0.935 ns) = 2.511 ns; Loc. = LC_X8_Y8_N5; Fanout = 581; REG Node = '16to8ddf:inst21\|lpm_tff1:inst5\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "2.511 ns" { altpll0:inst17|altpll:altpll_component|_clk0 16to8ddf:inst21|lpm_tff1:inst5|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/lpm_ff.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.183 ns) + CELL(0.711 ns) 6.405 ns 16to8ddf:inst21\|lpm_dff4:inst\|lpm_ff:lpm_ff_component\|dffs\[3\] 3 REG LC_X13_Y5_N2 1 " "Info: 3: + IC(3.183 ns) + CELL(0.711 ns) = 6.405 ns; Loc. = LC_X13_Y5_N2; Fanout = 1; REG Node = '16to8ddf:inst21\|lpm_dff4:inst\|lpm_ff:lpm_ff_component\|dffs\[3\]'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "3.894 ns" { 16to8ddf:inst21|lpm_tff1:inst5|lpm_ff:lpm_ff_component|dffs[0] 16to8ddf:inst21|lpm_dff4:inst|lpm_ff:lpm_ff_component|dffs[3] } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/lpm_ff.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 25.70 % " "Info: Total cell delay = 1.646 ns ( 25.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.759 ns 74.30 % " "Info: Total interconnect delay = 4.759 ns ( 74.30 % )" {  } {  } 0}  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "6.405 ns" { altpll0:inst17|altpll:altpll_component|_clk0 16to8ddf:inst21|lpm_tff1:inst5|lpm_ff:lpm_ff_component|dffs[0] 16to8ddf:inst21|lpm_dff4:inst|lpm_ff:lpm_ff_component|dffs[3] }