fifoasi.tan.qmsg

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

{ "Info" "ITAN_NO_REG2REG_EXIST" "ASICLK " "Info: No valid register-to-register paths exist for clock ASICLK" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "DSPCLK " "Info: No valid register-to-register paths exist for clock DSPCLK" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "DSPCLK pin CE\[0\] memory dsptoasi:inst40\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|dsptoasi_altsyncram_bv01:altsyncram1\|ram_block30a_15~porta_datain_reg15 3.34 ns " "Info: Slack time is 3.34 ns for clock DSPCLK between source pin CE\[0\] and destination memory dsptoasi:inst40\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|dsptoasi_altsyncram_bv01:altsyncram1\|ram_block30a_15~porta_datain_reg15" { { "Info" "ITDB_FULL_TSU_REQUIREMENT" "15.000 ns + memory " "Info: + tsu requirement for source pin and destination memory is 15.000 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TSU_RESULT" "11.660 ns - " "Info: - tsu from clock to input pin is 11.660 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.456 ns + Longest pin memory " "Info: + Longest pin to memory delay is 12.456 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CE\[0\] 1 PIN PIN_G1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_G1; Fanout = 1; PIN Node = 'CE\[0\]'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { CE[0] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -792 2184 2361 -776 "CE\[3..0\]" "" } { -800 1968 2184 -784 "CE\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.345 ns) + CELL(0.590 ns) 3.404 ns uncode:inst36\|reduce_nor~430 2 COMB LC_X1_Y13_N0 7 " "Info: 2: + IC(1.345 ns) + CELL(0.590 ns) = 3.404 ns; Loc. = LC_X1_Y13_N0; Fanout = 7; COMB Node = 'uncode:inst36\|reduce_nor~430'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "1.935 ns" { CE[0] uncode:inst36|reduce_nor~430 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.114 ns) 3.950 ns uncode:inst36\|reduce_nor~10 3 COMB LC_X1_Y13_N8 25 " "Info: 3: + IC(0.432 ns) + CELL(0.114 ns) = 3.950 ns; Loc. = LC_X1_Y13_N8; Fanout = 25; COMB Node = 'uncode:inst36\|reduce_nor~10'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "0.546 ns" { uncode:inst36|reduce_nor~430 uncode:inst36|reduce_nor~10 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.114 ns) 5.135 ns uncode:inst36\|IND\[7\]\$latch\$en_or~30 4 COMB LC_X1_Y13_N3 5 " "Info: 4: + IC(1.071 ns) + CELL(0.114 ns) = 5.135 ns; Loc. = LC_X1_Y13_N3; Fanout = 5; COMB Node = 'uncode:inst36\|IND\[7\]\$latch\$en_or~30'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "1.185 ns" { uncode:inst36|reduce_nor~10 uncode:inst36|IND[7]$latch$en_or~30 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.913 ns) + CELL(0.442 ns) 7.490 ns uncode:inst36\|INB\[7\]\$latch\$en_or 5 COMB LC_X9_Y14_N5 17 " "Info: 5: + IC(1.913 ns) + CELL(0.442 ns) = 7.490 ns; Loc. = LC_X9_Y14_N5; Fanout = 17; COMB Node = 'uncode:inst36\|INB\[7\]\$latch\$en_or'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "2.355 ns" { uncode:inst36|IND[7]$latch$en_or~30 uncode:inst36|INB[7]$latch$en_or } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.463 ns) + CELL(0.442 ns) 8.395 ns uncode:inst36\|always0_868~324 6 COMB LC_X9_Y14_N3 17 " "Info: 6: + IC(0.463 ns) + CELL(0.442 ns) = 8.395 ns; Loc. = LC_X9_Y14_N3; Fanout = 17; COMB Node = 'uncode:inst36\|always0_868~324'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "0.905 ns" { uncode:inst36|INB[7]$latch$en_or uncode:inst36|always0_868~324 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.599 ns) + CELL(0.292 ns) 10.286 ns uncode:inst36\|INB\[0\]~31 7 COMB LC_X13_Y15_N7 1 " "Info: 7: + IC(1.599 ns) + CELL(0.292 ns) = 10.286 ns; Loc. = LC_X13_Y15_N7; Fanout = 1; COMB Node = 'uncode:inst36\|INB\[0\]~31'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "1.891 ns" { uncode:inst36|always0_868~324 uncode:inst36|INB[0]~31 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 59 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.814 ns) + CELL(0.356 ns) 12.456 ns dsptoasi:inst40\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|dsptoasi_altsyncram_bv01:altsyncram1\|ram_block30a_15~porta_datain_reg15 8 MEM M4K_X15_Y14 1 " "Info: 8: + IC(1.814 ns) + CELL(0.356 ns) = 12.456 ns; Loc. = M4K_X15_Y14; Fanout = 1; MEM Node = 'dsptoasi:inst40\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|dsptoasi_altsyncram_bv01:altsyncram1\|ram_block30a_15~porta_datain_reg15'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "2.170 ns" { uncode:inst36|INB[0]~31 dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/dsptoasi.v" "" "" { Text "D:/altera9.16/9.16fifoasi/dsptoasi.v" 1489 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.819 ns 30.66 % " "Info: Total cell delay = 3.819 ns ( 30.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.637 ns 69.34 % " "Info: Total interconnect delay = 8.637 ns ( 69.34 % )" {  } {  } 0}  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "12.456 ns" { CE[0] uncode:inst36|reduce_nor~430 uncode:inst36|reduce_nor~10 uncode:inst36|IND[7]$latch$en_or~30 uncode:inst36|INB[7]$latch$en_or uncode:inst36|always0_868~324 uncode:inst36|INB[0]~31 dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_PLL_OFFSET" "DSPCLK altpll1:inst18\|altpll:altpll_component\|_clk1 -1.443 ns - " "Info: - Offset between input clock DSPCLK and output clock altpll1:inst18\|altpll:altpll_component\|_clk1 is -1.443 ns" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 1592 1744 1912 1608 "DSPCLK" "" } } } } { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 696 3 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "D:/altera9.16/9.16fifoasi/dsptoasi.v" "" "" { Text "D:/altera9.16/9.16fifoasi/dsptoasi.v" 1489 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll1:inst18\|altpll:altpll_component\|_clk1 destination 2.332 ns - Shortest memory " "Info: - Shortest clock path from clock altpll1:inst18\|altpll:altpll_component\|_clk1 to destination memory is 2.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll1:inst18\|altpll:altpll_component\|_clk1 1 CLK PLL_1 992 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 992; CLK Node = 'altpll1:inst18\|altpll:altpll_component\|_clk1'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { altpll1:inst18|altpll:altpll_component|_clk1 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 696 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.610 ns) + CELL(0.722 ns) 2.332 ns dsptoasi:inst40\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|dsptoasi_altsyncram_bv01:altsyncram1\|ram_block30a_15~porta_datain_reg15 2 MEM M4K_X15_Y14 1 " "Info: 2: + IC(1.610 ns) + CELL(0.722 ns) = 2.332 ns; Loc. = M4K_X15_Y14; Fanout = 1; MEM Node = 'dsptoasi:inst40\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|dsptoasi_altsyncram_bv01:altsyncram1\|ram_block30a_15~porta_datain_reg15'" {  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "2.332 ns" { altpll1:inst18|altpll:altpll_component|_clk1 dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/dsptoasi.v" "" "" { Text "D:/altera9.16/9.16fifoasi/dsptoasi.v" 1489 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns 30.96 % " "Info: Total cell delay = 0.722 ns ( 30.96 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.610 ns 69.04 % " "Info: Total interconnect delay = 1.610 ns ( 69.04 % )" {  } {  } 0}  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "2.332 ns" { altpll1:inst18|altpll:altpll_component|_clk1 dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 } "NODE_NAME" } } }  } 0}  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "12.456 ns" { CE[0] uncode:inst36|reduce_nor~430 uncode:inst36|reduce_nor~10 uncode:inst36|IND[7]$latch$en_or~30 uncode:inst36|INB[7]$latch$en_or uncode:inst36|always0_868~324 uncode:inst36|INB[0]~31 dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "2.332 ns" { altpll1:inst18|altpll:altpll_component|_clk1 dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 } "NODE_NAME" } } }  } 0}  } { { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "12.456 ns" { CE[0] uncode:inst36|reduce_nor~430 uncode:inst36|reduce_nor~10 uncode:inst36|IND[7]$latch$en_or~30 uncode:inst36|INB[7]$latch$en_or uncode:inst36|always0_868~324 uncode:inst36|INB[0]~31 dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "2.332 ns" { altpll1:inst18|altpll:altpll_component|_clk1 dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 } "NODE_NAME" } } }  } 0}