fifoasi.sim.qmsg

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 24 18:11:38 2004 " "Info: Processing started: Fri Sep 24 18:11:38 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --import_settings_files=on --export_settings_files=off fifoasi -c fifoasi " "Info: Command: quartus_sim --import_settings_files=on --export_settings_files=off fifoasi -c fifoasi" {  } {  } 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "dsptoasi:inst41\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|scfifo:scfifo14\|a_fffifo:subfifo\|a_fefifo:fifo_state\|b_full " "Warning: Can't display state machine states -- register holding state machine bit dsptoasi:inst41\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|scfifo:scfifo14\|a_fffifo:subfifo\|a_fefifo:fifo_state\|b_full was synthesized away" {  } { { "c:/altera/quartus41/libraries/megafunctions/a_fefifo.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/a_fefifo.tdf" 90 4 0 } }  } 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "dsptoasi:inst40\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|scfifo:scfifo14\|a_fffifo:subfifo\|a_fefifo:fifo_state\|b_full " "Warning: Can't display state machine states -- register holding state machine bit dsptoasi:inst40\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|scfifo:scfifo14\|a_fffifo:subfifo\|a_fefifo:fifo_state\|b_full was synthesized away" {  } { { "c:/altera/quartus41/libraries/megafunctions/a_fefifo.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/a_fefifo.tdf" 90 4 0 } }  } 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "dsptoasi:inst38\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|scfifo:scfifo14\|a_fffifo:subfifo\|a_fefifo:fifo_state\|b_full " "Warning: Can't display state machine states -- register holding state machine bit dsptoasi:inst38\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|scfifo:scfifo14\|a_fffifo:subfifo\|a_fefifo:fifo_state\|b_full was synthesized away" {  } { { "c:/altera/quartus41/libraries/megafunctions/a_fefifo.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/a_fefifo.tdf" 90 4 0 } }  } 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "dsptoasi:inst39\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|scfifo:scfifo14\|a_fffifo:subfifo\|a_fefifo:fifo_state\|b_full " "Warning: Can't display state machine states -- register holding state machine bit dsptoasi:inst39\|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component\|scfifo:scfifo14\|a_fffifo:subfifo\|a_fefifo:fifo_state\|b_full was synthesized away" {  } { { "c:/altera/quartus41/libraries/megafunctions/a_fefifo.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/a_fefifo.tdf" 90 4 0 } }  } 0}
{ "Error" "ESIM_NO_VECTOR_FILE_FOUND" "D:/altera9.16/9.16fifoasi/fifoasi.vwf " "Error: No valid vector source file specified and default file D:/altera9.16/9.16fifoasi/fifoasi.vwf does not exist" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Simulator 1  4 s " "Error: Quartus II Simulator was unsuccessful. 1 error, 4 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Fri Sep 24 18:11:40 2004 " "Error: Processing ended: Fri Sep 24 18:11:40 2004" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}