fifoasi.fit.qmsg

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "11 " "Info: Fitter routing operations ending: elapsed time = 11 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "17 " "Warning: Following 17 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LPEN VCC " "Info: Pin LPEN has VCC driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 24 2600 2776 40 "LPEN" "" } { 16 2376 2400 88 "LPEN" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "LPEN" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { LPEN } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { LPEN } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SDASEL GND " "Info: Pin SDASEL has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 112 2600 2776 128 "SDASEL" "" } { 104 2536 2600 120 "SDASEL" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SDASEL" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { SDASEL } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { SDASEL } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DECMODE VCC " "Info: Pin DECMODE has VCC driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 136 2600 2776 152 "DECMODE" "" } { 128 2536 2600 144 "DECMODE" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DECMODE" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { DECMODE } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { DECMODE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "BISTLE VCC " "Info: Pin BISTLE has VCC driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 216 2600 2776 232 "BISTLE" "" } { 208 2536 2600 224 "BISTLE" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "BISTLE" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { BISTLE } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { BISTLE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RXLE VCC " "Info: Pin RXLE has VCC driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 240 2600 2776 256 "RXLE" "" } { 232 2536 2600 248 "RXLE" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "RXLE" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { RXLE } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { RXLE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OELE VCC " "Info: Pin OELE has VCC driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 264 2592 2768 280 "OELE" "" } { 256 2536 2592 272 "OELE" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "OELE" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { OELE } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { OELE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SCSEL GND " "Info: Pin SCSEL has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 288 2600 2776 304 "SCSEL" "" } { 280 2536 2600 296 "SCSEL" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SCSEL" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { SCSEL } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { SCSEL } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RXMODE0 GND " "Info: Pin RXMODE0 has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 312 2600 2776 328 "RXMODE0" "" } { 304 2536 2600 320 "RXMODE0" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "RXMODE0" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { RXMODE0 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { RXMODE0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RXMODE1 GND " "Info: Pin RXMODE1 has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 336 2600 2776 352 "RXMODE1" "" } { 328 2536 2600 344 "RXMODE1" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "RXMODE1" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { RXMODE1 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { RXMODE1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXMODE0 GND " "Info: Pin TXMODE0 has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 400 2600 2776 416 "TXMODE0" "" } { 366 2456 2472 415 "TXMODE0" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "TXMODE0" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { TXMODE0 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { TXMODE0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXMODE1 GND " "Info: Pin TXMODE1 has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 432 2592 2768 448 "TXMODE1" "" } { 368 2368 2410 440 "TXMODE1" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "TXMODE1" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { TXMODE1 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { TXMODE1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "BOND_INH GND " "Info: Pin BOND_INH has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 184 2600 2776 200 "BOND_INH" "" } { 176 2536 2603 192 "BOND_INH" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "BOND_INH" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { BOND_INH } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { BOND_INH } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXRST VCC " "Info: Pin TXRST has VCC driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 56 2600 2776 72 "TXRST" "" } { 44 2432 2448 88 "TXRST" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "TXRST" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { TXRST } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { TXRST } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXCTABCD\[0\] GND " "Info: Pin TXCTABCD\[0\] has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 248 88 265 264 "TXCTABCD\[0..3\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "TXCTABCD\[0\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { TXCTABCD[0] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { TXCTABCD[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXCTABCD\[1\] GND " "Info: Pin TXCTABCD\[1\] has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 248 88 265 264 "TXCTABCD\[0..3\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "TXCTABCD\[1\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { TXCTABCD[1] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { TXCTABCD[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXCTABCD\[2\] GND " "Info: Pin TXCTABCD\[2\] has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 248 88 265 264 "TXCTABCD\[0..3\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "TXCTABCD\[2\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { TXCTABCD[2] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { TXCTABCD[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXCTABCD\[3\] GND " "Info: Pin TXCTABCD\[3\] has GND driving its datain port" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 248 88 265 264 "TXCTABCD\[0..3\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "TXCTABCD\[3\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { TXCTABCD[3] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { TXCTABCD[3] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "uncode:inst36\|always0_2404~74 " "Info: Following pins have the same output enable: uncode:inst36\|always0_2404~74" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[15\] LVTTL " "Info: Type bidirectional pin dspio\[15\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[15\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[15] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[15] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[14\] LVTTL " "Info: Type bidirectional pin dspio\[14\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[14\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[14] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[14] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[13\] LVTTL " "Info: Type bidirectional pin dspio\[13\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[13\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[13] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[12\] LVTTL " "Info: Type bidirectional pin dspio\[12\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[12\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[12] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[12] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[11\] LVTTL " "Info: Type bidirectional pin dspio\[11\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[11\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[11] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[10\] LVTTL " "Info: Type bidirectional pin dspio\[10\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[10\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[10] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[9\] LVTTL " "Info: Type bidirectional pin dspio\[9\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[9\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[9] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[8\] LVTTL " "Info: Type bidirectional pin dspio\[8\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[8\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[8] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[7\] LVTTL " "Info: Type bidirectional pin dspio\[7\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[7\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[7] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[6\] LVTTL " "Info: Type bidirectional pin dspio\[6\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[6\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[6] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[5\] LVTTL " "Info: Type bidirectional pin dspio\[5\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[5\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[5] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[4\] LVTTL " "Info: Type bidirectional pin dspio\[4\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[4\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[4] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[3\] LVTTL " "Info: Type bidirectional pin dspio\[3\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[3\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[3] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[2\] LVTTL " "Info: Type bidirectional pin dspio\[2\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[2\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[2] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[1\] LVTTL " "Info: Type bidirectional pin dspio\[1\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[1\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[1] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dspio\[0\] LVTTL " "Info: Type bidirectional pin dspio\[0\] uses the LVTTL I/O standard" {  } { { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { -600 2216 2392 -584 "dspio\[15..0\]" "" } { -608 1968 2216 -592 "DSPIO\[15..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "dspio\[0\]" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { dspio[0] } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { dspio[0] } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 24 18:09:23 2004 " "Info: Processing ended: Fri Sep 24 18:09:23 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:12 " "Info: Elapsed time: 00:01:12" {  } {  } 0}  } {  } 0}