fifoasi.fit.qmsg

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 24 18:08:11 2004 " "Info: Processing started: Fri Sep 24 18:08:11 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off fifoasi -c fifoasi " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off fifoasi -c fifoasi" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "fifoasi EP1C4F324C8 " "Info: Selected device EP1C4F324C8 for design fifoasi" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "altpll1:inst18\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL altpll1:inst18\|altpll:altpll_component\|pll" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll1:inst18\|altpll:altpll_component\|_clk1 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll1:inst18\|altpll:altpll_component\|_clk1 port" {  } {  } 0}  } { { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 699 3 0 } } { "D:/altera9.16/9.16fifoasi/altpll1.v" "" "" { Text "D:/altera9.16/9.16fifoasi/altpll1.v" 56 -1 0 } } { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 1536 1472 1744 1696 "inst18" "" } } } }  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "altpll0:inst17\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL altpll0:inst17\|altpll:altpll_component\|pll" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll0:inst17\|altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll0:inst17\|altpll:altpll_component\|_clk0 port" {  } {  } 0}  } { { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 699 3 0 } } { "D:/altera9.16/9.16fifoasi/altpll0.tdf" "" "" { Text "D:/altera9.16/9.16fifoasi/altpll0.tdf" 50 2 0 } } { "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" "" "" { Schematic "D:/altera9.16/9.16fifoasi/fifo_asi.bdf" { { 1592 232 504 1752 "inst17" "" } } } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12F324C8 " "Info: Device EP1C12F324C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C20F324C8 " "Info: Device EP1C20F324C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "altpll1:inst18\|altpll:altpll_component\|_clk1 " "Info: Promoted signal altpll1:inst18\|altpll:altpll_component\|_clk1 to use global clock" {  } { { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 699 3 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altpll1:inst18\|altpll:altpll_component\|_clk0" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { altpll1:inst18|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { altpll1:inst18|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "altpll0:inst17\|altpll:altpll_component\|_clk0 " "Info: Promoted signal altpll0:inst17\|altpll:altpll_component\|_clk0 to use global clock" {  } { { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 699 3 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altpll0:inst17\|altpll:altpll_component\|_clk0" } } } } { "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" "" "" { Report "D:/altera9.16/9.16fifoasi/db/fifoasi_cmp.qrpt" Compiler "fifoasi" "UNKNOWN" "V1" "D:/altera9.16/9.16fifoasi/db/fifoasi.quartus_db" { Floorplan "" "" "" { altpll0:inst17|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { Floorplan "D:/altera9.16/9.16fifoasi/fifoasi.fld" "" "" { altpll0:inst17|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}