fifoasi.map.qmsg

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" "altpll" "" { Text "c:/altera/quartus41/libraries/megafunctions/altpll.tdf" 310 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SOE3 uncode.v(101) " "Warning: Verilog HDL Always Construct warning at uncode.v(101): variable SOE3 is used in Always Construct, but isn't in the Always Construct's Event Control" {  } { { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 101 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "LFI uncode.v(127) " "Warning: Verilog HDL Always Construct warning at uncode.v(127): variable LFI is used in Always Construct, but isn't in the Always Construct's Event Control" {  } { { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 127 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "INA uncode.v(100) " "Warning: Verilog HDL Always Construct warning at uncode.v(100): variable INA may not be assigned a new value in every possible path through the Always Construct.  Variable INA holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "INB uncode.v(100) " "Warning: Verilog HDL Always Construct warning at uncode.v(100): variable INB may not be assigned a new value in every possible path through the Always Construct.  Variable INB holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "INC uncode.v(100) " "Warning: Verilog HDL Always Construct warning at uncode.v(100): variable INC may not be assigned a new value in every possible path through the Always Construct.  Variable INC holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "IND uncode.v(100) " "Warning: Verilog HDL Always Construct warning at uncode.v(100): variable IND may not be assigned a new value in every possible path through the Always Construct.  Variable IND holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "INE uncode.v(100) " "Warning: Verilog HDL Always Construct warning at uncode.v(100): variable INE may not be assigned a new value in every possible path through the Always Construct.  Variable INE holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "DSPIO uncode.v(100) " "Warning: Verilog HDL Always Construct warning at uncode.v(100): variable DSPIO may not be assigned a new value in every possible path through the Always Construct.  Variable DSPIO holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/altera9.16/9.16fifoasi/uncode.v" "" "" { Text "D:/altera9.16/9.16fifoasi/uncode.v" 100 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "altpll1.v 1 1 " "Info: Using design file altpll1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 altpll1 " "Info: Found entity 1: altpll1" {  } { { "D:/altera9.16/9.16fifoasi/altpll1.v" "altpll1" "" { Text "D:/altera9.16/9.16fifoasi/altpll1.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lpm_dff1.v 1 1 " "Info: Using design file lpm_dff1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_dff1 " "Info: Found entity 1: lpm_dff1" {  } { { "D:/altera9.16/9.16fifoasi/lpm_dff1.v" "lpm_dff1" "" { Text "D:/altera9.16/9.16fifoasi/lpm_dff1.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lpm_tff1.v 1 1 " "Info: Using design file lpm_tff1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_tff1 " "Info: Found entity 1: lpm_tff1" {  } { { "D:/altera9.16/9.16fifoasi/lpm_tff1.v" "lpm_tff1" "" { Text "D:/altera9.16/9.16fifoasi/lpm_tff1.v" 42 -1 0 } }  } 0}  } {  } 0}