fifoasi.hier_info

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|add_sub_fub:add_sub5
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|cntr_uu7:cntr10
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
clk_en => counter_cella0.ENA
clk_en => counter_cella1.ENA
clk_en => counter_cella2.ENA
clk_en => counter_cella3.ENA
clk_en => counter_cella4.ENA
clk_en => counter_cella5.ENA
clk_en => counter_cella6.ENA
clk_en => counter_cella7.ENA
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
cout <= counter_cella7.COUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|cntr_uu7:cntr4
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
clk_en => counter_cella0.ENA
clk_en => counter_cella1.ENA
clk_en => counter_cella2.ENA
clk_en => counter_cella3.ENA
clk_en => counter_cella4.ENA
clk_en => counter_cella5.ENA
clk_en => counter_cella6.ENA
clk_en => counter_cella7.ENA
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
cout <= counter_cella7.COUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|scfifo:scfifo14
data[0] => a_fffifo:subfifo.data[0]
data[1] => a_fffifo:subfifo.data[1]
data[2] => a_fffifo:subfifo.data[2]
data[3] => a_fffifo:subfifo.data[3]
data[4] => a_fffifo:subfifo.data[4]
data[5] => a_fffifo:subfifo.data[5]
data[6] => a_fffifo:subfifo.data[6]
data[7] => a_fffifo:subfifo.data[7]
data[8] => a_fffifo:subfifo.data[8]
data[9] => a_fffifo:subfifo.data[9]
data[10] => a_fffifo:subfifo.data[10]
data[11] => a_fffifo:subfifo.data[11]
data[12] => a_fffifo:subfifo.data[12]
data[13] => a_fffifo:subfifo.data[13]
data[14] => a_fffifo:subfifo.data[14]
data[15] => a_fffifo:subfifo.data[15]
q[0] <= a_fffifo:subfifo.q[0]
q[1] <= a_fffifo:subfifo.q[1]
q[2] <= a_fffifo:subfifo.q[2]
q[3] <= a_fffifo:subfifo.q[3]
q[4] <= a_fffifo:subfifo.q[4]
q[5] <= a_fffifo:subfifo.q[5]
q[6] <= a_fffifo:subfifo.q[6]
q[7] <= a_fffifo:subfifo.q[7]
q[8] <= a_fffifo:subfifo.q[8]
q[9] <= a_fffifo:subfifo.q[9]
q[10] <= a_fffifo:subfifo.q[10]
q[11] <= a_fffifo:subfifo.q[11]
q[12] <= a_fffifo:subfifo.q[12]
q[13] <= a_fffifo:subfifo.q[13]
q[14] <= a_fffifo:subfifo.q[14]
q[15] <= a_fffifo:subfifo.q[15]
wrreq => a_fffifo:subfifo.wreq
rdreq => a_fffifo:subfifo.rreq
clock => a_fffifo:subfifo.clock
aclr => a_fffifo:subfifo.aclr
sclr => a_fffifo:subfifo.sclr
empty <= a_fffifo:subfifo.empty
full <= a_fffifo:subfifo.full
almost_full <= <UNC>
almost_empty <= <UNC>
usedw[0] <= a_fffifo:subfifo.usedw[0]
usedw[1] <= a_fffifo:subfifo.usedw[1]


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|scfifo:scfifo14|a_fffifo:subfifo
data[0] => lpm_ff:data_node[0][0].data[0]
data[0] => lpm_ff:data_node[0][1].data[0]
data[1] => lpm_ff:data_node[0][0].data[1]
data[1] => lpm_ff:data_node[0][1].data[1]
data[2] => lpm_ff:data_node[0][0].data[2]
data[2] => lpm_ff:data_node[0][1].data[2]
data[3] => lpm_ff:data_node[0][0].data[3]
data[3] => lpm_ff:data_node[0][1].data[3]
data[4] => lpm_ff:data_node[0][0].data[4]
data[4] => lpm_ff:data_node[0][1].data[4]
data[5] => lpm_ff:data_node[0][0].data[5]
data[5] => lpm_ff:data_node[0][1].data[5]
data[6] => lpm_ff:data_node[0][0].data[6]
data[6] => lpm_ff:data_node[0][1].data[6]
data[7] => lpm_ff:data_node[0][0].data[7]
data[7] => lpm_ff:data_node[0][1].data[7]
data[8] => lpm_ff:data_node[0][0].data[8]
data[8] => lpm_ff:data_node[0][1].data[8]
data[9] => lpm_ff:data_node[0][0].data[9]
data[9] => lpm_ff:data_node[0][1].data[9]
data[10] => lpm_ff:data_node[0][0].data[10]
data[10] => lpm_ff:data_node[0][1].data[10]
data[11] => lpm_ff:data_node[0][0].data[11]
data[11] => lpm_ff:data_node[0][1].data[11]
data[12] => lpm_ff:data_node[0][0].data[12]
data[12] => lpm_ff:data_node[0][1].data[12]
data[13] => lpm_ff:data_node[0][0].data[13]
data[13] => lpm_ff:data_node[0][1].data[13]
data[14] => lpm_ff:data_node[0][0].data[14]
data[14] => lpm_ff:data_node[0][1].data[14]
data[15] => lpm_ff:data_node[0][0].data[15]
data[15] => lpm_ff:data_node[0][1].data[15]
q[0] <= lpm_ff:output_buffer.q[0]
q[1] <= lpm_ff:output_buffer.q[1]
q[2] <= lpm_ff:output_buffer.q[2]
q[3] <= lpm_ff:output_buffer.q[3]
q[4] <= lpm_ff:output_buffer.q[4]
q[5] <= lpm_ff:output_buffer.q[5]
q[6] <= lpm_ff:output_buffer.q[6]
q[7] <= lpm_ff:output_buffer.q[7]
q[8] <= lpm_ff:output_buffer.q[8]
q[9] <= lpm_ff:output_buffer.q[9]
q[10] <= lpm_ff:output_buffer.q[10]
q[11] <= lpm_ff:output_buffer.q[11]
q[12] <= lpm_ff:output_buffer.q[12]
q[13] <= lpm_ff:output_buffer.q[13]
q[14] <= lpm_ff:output_buffer.q[14]
q[15] <= lpm_ff:output_buffer.q[15]
wreq => valid_wreq.IN0
wreq => a_fefifo:fifo_state.wreq
rreq => valid_rreq.IN0
rreq => a_fefifo:fifo_state.rreq
clock => lpm_ff:data_node[0][1].clock
clock => lpm_ff:data_node[0][0].clock
clock => lpm_ff:last_data_node[1].clock
clock => lpm_ff:last_data_node[0].clock
clock => lpm_counter:rd_ptr.clock
clock => lpm_ff:output_buffer.clock
clock => a_fefifo:fifo_state.clock
aclr => a_fefifo:fifo_state.aclr
aclr => lpm_ff:data_node[0][1].aclr
aclr => lpm_ff:data_node[0][0].aclr
aclr => lpm_ff:last_data_node[1].aclr
aclr => lpm_ff:last_data_node[0].aclr
aclr => lpm_counter:rd_ptr.aclr
aclr => lpm_ff:output_buffer.aclr
sclr => lpm_counter:rd_ptr.sclr
sclr => a_fefifo:fifo_state.sclr
threshlevel[0] => ~NO_FANOUT~
threshlevel[1] => ~NO_FANOUT~
threshold <= a_fefifo:fifo_state.threshold
empty <= a_fefifo:fifo_state.empty
full <= a_fefifo:fifo_state.full
usedw[0] <= lpm_counter:rd_ptr.q[0]
usedw[1] <= lpm_counter:rd_ptr.q[1]


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|scfifo:scfifo14|a_fffifo:subfifo|lpm_ff:data_node[0][1]
clock => dffs[15].CLK
clock => dffs[14].CLK
clock => dffs[13].CLK
clock => dffs[12].CLK
clock => dffs[11].CLK
clock => dffs[10].CLK
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[15].ENA
enable => dffs[14].ENA
enable => dffs[13].ENA
enable => dffs[12].ENA
enable => dffs[11].ENA
enable => dffs[10].ENA
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffs[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffs[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffs[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= dffs[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= dffs[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= dffs[15].DB_MAX_OUTPUT_PORT_TYPE


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|scfifo:scfifo14|a_fffifo:subfifo|lpm_ff:data_node[0][0]
clock => dffs[15].CLK
clock => dffs[14].CLK
clock => dffs[13].CLK
clock => dffs[12].CLK
clock => dffs[11].CLK
clock => dffs[10].CLK
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[15].ENA
enable => dffs[14].ENA
enable => dffs[13].ENA
enable => dffs[12].ENA
enable => dffs[11].ENA
enable => dffs[10].ENA
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffs[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffs[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffs[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= dffs[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= dffs[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= dffs[15].DB_MAX_OUTPUT_PORT_TYPE


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|scfifo:scfifo14|a_fffifo:subfifo|lpm_mux:row_data_out_mux[0]
data[0][0] => mux_pgc:auto_generated.data[0]
data[0][1] => mux_pgc:auto_generated.data[1]
data[0][2] => mux_pgc:auto_generated.data[2]
data[0][3] => mux_pgc:auto_generated.data[3]
data[0][4] => mux_pgc:auto_generated.data[4]
data[0][5] => mux_pgc:auto_generated.data[5]
data[0][6] => mux_pgc:auto_generated.data[6]
data[0][7] => mux_pgc:auto_generated.data[7]
data[0][8] => mux_pgc:auto_generated.data[8]
data[0][9] => mux_pgc:auto_generated.data[9]
data[0][10] => mux_pgc:auto_generated.data[10]
data[0][11] => mux_pgc:auto_generated.data[11]
data[0][12] => mux_pgc:auto_generated.data[12]
data[0][13] => mux_pgc:auto_generated.data[13]
data[0][14] => mux_pgc:auto_generated.data[14]
data[0][15] => mux_pgc:auto_generated.data[15]
data[1][0] => mux_pgc:auto_generated.data[16]
data[1][1] => mux_pgc:auto_generated.data[17]
data[1][2] => mux_pgc:auto_generated.data[18]
data[1][3] => mux_pgc:auto_generated.data[19]
data[1][4] => mux_pgc:auto_generated.data[20]
data[1][5] => mux_pgc:auto_generated.data[21]
data[1][6] => mux_pgc:auto_generated.data[22]
data[1][7] => mux_pgc:auto_generated.data[23]
data[1][8] => mux_pgc:auto_generated.data[24]
data[1][9] => mux_pgc:auto_generated.data[25]
data[1][10] => mux_pgc:auto_generated.data[26]
data[1][11] => mux_pgc:auto_generated.data[27]
data[1][12] => mux_pgc:auto_generated.data[28]
data[1][13] => mux_pgc:auto_generated.data[29]
data[1][14] => mux_pgc:auto_generated.data[30]
data[1][15] => mux_pgc:auto_generated.data[31]
sel[0] => mux_pgc:auto_generated.sel[0]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_pgc:auto_generated.result[0]
result[1] <= mux_pgc:auto_generated.result[1]
result[2] <= mux_pgc:auto_generated.result[2]
result[3] <= mux_pgc:auto_generated.result[3]
result[4] <= mux_pgc:auto_generated.result[4]
result[5] <= mux_pgc:auto_generated.result[5]
result[6] <= mux_pgc:auto_generated.result[6]
result[7] <= mux_pgc:auto_generated.result[7]
result[8] <= mux_pgc:auto_generated.result[8]
result[9] <= mux_pgc:auto_generated.result[9]
result[10] <= mux_pgc:auto_generated.result[10]
result[11] <= mux_pgc:auto_generated.result[11]
result[12] <= mux_pgc:auto_generated.result[12]
result[13] <= mux_pgc:auto_generated.result[13]
result[14] <= mux_pgc:auto_generated.result[14]
result[15] <= mux_pgc:auto_generated.result[15]