fifoasi.hier_info

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

address_b[1] => ram_block30a1.PORTBADDR1
address_b[1] => ram_block30a2.PORTBADDR1
address_b[1] => ram_block30a3.PORTBADDR1
address_b[1] => ram_block30a4.PORTBADDR1
address_b[1] => ram_block30a5.PORTBADDR1
address_b[1] => ram_block30a6.PORTBADDR1
address_b[1] => ram_block30a7.PORTBADDR1
address_b[1] => ram_block30a8.PORTBADDR1
address_b[1] => ram_block30a9.PORTBADDR1
address_b[1] => ram_block30a10.PORTBADDR1
address_b[1] => ram_block30a11.PORTBADDR1
address_b[1] => ram_block30a12.PORTBADDR1
address_b[1] => ram_block30a13.PORTBADDR1
address_b[1] => ram_block30a14.PORTBADDR1
address_b[1] => ram_block30a15.PORTBADDR1
address_b[2] => ram_block30a0.PORTBADDR2
address_b[2] => ram_block30a1.PORTBADDR2
address_b[2] => ram_block30a2.PORTBADDR2
address_b[2] => ram_block30a3.PORTBADDR2
address_b[2] => ram_block30a4.PORTBADDR2
address_b[2] => ram_block30a5.PORTBADDR2
address_b[2] => ram_block30a6.PORTBADDR2
address_b[2] => ram_block30a7.PORTBADDR2
address_b[2] => ram_block30a8.PORTBADDR2
address_b[2] => ram_block30a9.PORTBADDR2
address_b[2] => ram_block30a10.PORTBADDR2
address_b[2] => ram_block30a11.PORTBADDR2
address_b[2] => ram_block30a12.PORTBADDR2
address_b[2] => ram_block30a13.PORTBADDR2
address_b[2] => ram_block30a14.PORTBADDR2
address_b[2] => ram_block30a15.PORTBADDR2
address_b[3] => ram_block30a0.PORTBADDR3
address_b[3] => ram_block30a1.PORTBADDR3
address_b[3] => ram_block30a2.PORTBADDR3
address_b[3] => ram_block30a3.PORTBADDR3
address_b[3] => ram_block30a4.PORTBADDR3
address_b[3] => ram_block30a5.PORTBADDR3
address_b[3] => ram_block30a6.PORTBADDR3
address_b[3] => ram_block30a7.PORTBADDR3
address_b[3] => ram_block30a8.PORTBADDR3
address_b[3] => ram_block30a9.PORTBADDR3
address_b[3] => ram_block30a10.PORTBADDR3
address_b[3] => ram_block30a11.PORTBADDR3
address_b[3] => ram_block30a12.PORTBADDR3
address_b[3] => ram_block30a13.PORTBADDR3
address_b[3] => ram_block30a14.PORTBADDR3
address_b[3] => ram_block30a15.PORTBADDR3
address_b[4] => ram_block30a0.PORTBADDR4
address_b[4] => ram_block30a1.PORTBADDR4
address_b[4] => ram_block30a2.PORTBADDR4
address_b[4] => ram_block30a3.PORTBADDR4
address_b[4] => ram_block30a4.PORTBADDR4
address_b[4] => ram_block30a5.PORTBADDR4
address_b[4] => ram_block30a6.PORTBADDR4
address_b[4] => ram_block30a7.PORTBADDR4
address_b[4] => ram_block30a8.PORTBADDR4
address_b[4] => ram_block30a9.PORTBADDR4
address_b[4] => ram_block30a10.PORTBADDR4
address_b[4] => ram_block30a11.PORTBADDR4
address_b[4] => ram_block30a12.PORTBADDR4
address_b[4] => ram_block30a13.PORTBADDR4
address_b[4] => ram_block30a14.PORTBADDR4
address_b[4] => ram_block30a15.PORTBADDR4
address_b[5] => ram_block30a0.PORTBADDR5
address_b[5] => ram_block30a1.PORTBADDR5
address_b[5] => ram_block30a2.PORTBADDR5
address_b[5] => ram_block30a3.PORTBADDR5
address_b[5] => ram_block30a4.PORTBADDR5
address_b[5] => ram_block30a5.PORTBADDR5
address_b[5] => ram_block30a6.PORTBADDR5
address_b[5] => ram_block30a7.PORTBADDR5
address_b[5] => ram_block30a8.PORTBADDR5
address_b[5] => ram_block30a9.PORTBADDR5
address_b[5] => ram_block30a10.PORTBADDR5
address_b[5] => ram_block30a11.PORTBADDR5
address_b[5] => ram_block30a12.PORTBADDR5
address_b[5] => ram_block30a13.PORTBADDR5
address_b[5] => ram_block30a14.PORTBADDR5
address_b[5] => ram_block30a15.PORTBADDR5
address_b[6] => ram_block30a0.PORTBADDR6
address_b[6] => ram_block30a1.PORTBADDR6
address_b[6] => ram_block30a2.PORTBADDR6
address_b[6] => ram_block30a3.PORTBADDR6
address_b[6] => ram_block30a4.PORTBADDR6
address_b[6] => ram_block30a5.PORTBADDR6
address_b[6] => ram_block30a6.PORTBADDR6
address_b[6] => ram_block30a7.PORTBADDR6
address_b[6] => ram_block30a8.PORTBADDR6
address_b[6] => ram_block30a9.PORTBADDR6
address_b[6] => ram_block30a10.PORTBADDR6
address_b[6] => ram_block30a11.PORTBADDR6
address_b[6] => ram_block30a12.PORTBADDR6
address_b[6] => ram_block30a13.PORTBADDR6
address_b[6] => ram_block30a14.PORTBADDR6
address_b[6] => ram_block30a15.PORTBADDR6
address_b[7] => ram_block30a0.PORTBADDR7
address_b[7] => ram_block30a1.PORTBADDR7
address_b[7] => ram_block30a2.PORTBADDR7
address_b[7] => ram_block30a3.PORTBADDR7
address_b[7] => ram_block30a4.PORTBADDR7
address_b[7] => ram_block30a5.PORTBADDR7
address_b[7] => ram_block30a6.PORTBADDR7
address_b[7] => ram_block30a7.PORTBADDR7
address_b[7] => ram_block30a8.PORTBADDR7
address_b[7] => ram_block30a9.PORTBADDR7
address_b[7] => ram_block30a10.PORTBADDR7
address_b[7] => ram_block30a11.PORTBADDR7
address_b[7] => ram_block30a12.PORTBADDR7
address_b[7] => ram_block30a13.PORTBADDR7
address_b[7] => ram_block30a14.PORTBADDR7
address_b[7] => ram_block30a15.PORTBADDR7
clock0 => ram_block30a0.CLK0
clock0 => ram_block30a1.CLK0
clock0 => ram_block30a2.CLK0
clock0 => ram_block30a3.CLK0
clock0 => ram_block30a4.CLK0
clock0 => ram_block30a5.CLK0
clock0 => ram_block30a6.CLK0
clock0 => ram_block30a7.CLK0
clock0 => ram_block30a8.CLK0
clock0 => ram_block30a9.CLK0
clock0 => ram_block30a10.CLK0
clock0 => ram_block30a11.CLK0
clock0 => ram_block30a12.CLK0
clock0 => ram_block30a13.CLK0
clock0 => ram_block30a14.CLK0
clock0 => ram_block30a15.CLK0
clock1 => ram_block30a0.CLK1
clock1 => ram_block30a1.CLK1
clock1 => ram_block30a2.CLK1
clock1 => ram_block30a3.CLK1
clock1 => ram_block30a4.CLK1
clock1 => ram_block30a5.CLK1
clock1 => ram_block30a6.CLK1
clock1 => ram_block30a7.CLK1
clock1 => ram_block30a8.CLK1
clock1 => ram_block30a9.CLK1
clock1 => ram_block30a10.CLK1
clock1 => ram_block30a11.CLK1
clock1 => ram_block30a12.CLK1
clock1 => ram_block30a13.CLK1
clock1 => ram_block30a14.CLK1
clock1 => ram_block30a15.CLK1
clocken1 => ram_block30a0.ENA1
clocken1 => ram_block30a1.ENA1
clocken1 => ram_block30a2.ENA1
clocken1 => ram_block30a3.ENA1
clocken1 => ram_block30a4.ENA1
clocken1 => ram_block30a5.ENA1
clocken1 => ram_block30a6.ENA1
clocken1 => ram_block30a7.ENA1
clocken1 => ram_block30a8.ENA1
clocken1 => ram_block30a9.ENA1
clocken1 => ram_block30a10.ENA1
clocken1 => ram_block30a11.ENA1
clocken1 => ram_block30a12.ENA1
clocken1 => ram_block30a13.ENA1
clocken1 => ram_block30a14.ENA1
clocken1 => ram_block30a15.ENA1
data_a[0] => ram_block30a0.PORTADATAIN
data_a[1] => ram_block30a1.PORTADATAIN
data_a[2] => ram_block30a2.PORTADATAIN
data_a[3] => ram_block30a3.PORTADATAIN
data_a[4] => ram_block30a4.PORTADATAIN
data_a[5] => ram_block30a5.PORTADATAIN
data_a[6] => ram_block30a6.PORTADATAIN
data_a[7] => ram_block30a7.PORTADATAIN
data_a[8] => ram_block30a8.PORTADATAIN
data_a[9] => ram_block30a9.PORTADATAIN
data_a[10] => ram_block30a10.PORTADATAIN
data_a[11] => ram_block30a11.PORTADATAIN
data_a[12] => ram_block30a12.PORTADATAIN
data_a[13] => ram_block30a13.PORTADATAIN
data_a[14] => ram_block30a14.PORTADATAIN
data_a[15] => ram_block30a15.PORTADATAIN
q_b[0] <= ram_block30a0.PORTBDATAOUT
q_b[1] <= ram_block30a1.PORTBDATAOUT
q_b[2] <= ram_block30a2.PORTBDATAOUT
q_b[3] <= ram_block30a3.PORTBDATAOUT
q_b[4] <= ram_block30a4.PORTBDATAOUT
q_b[5] <= ram_block30a5.PORTBDATAOUT
q_b[6] <= ram_block30a6.PORTBDATAOUT
q_b[7] <= ram_block30a7.PORTBDATAOUT
q_b[8] <= ram_block30a8.PORTBDATAOUT
q_b[9] <= ram_block30a9.PORTBDATAOUT
q_b[10] <= ram_block30a10.PORTBDATAOUT
q_b[11] <= ram_block30a11.PORTBDATAOUT
q_b[12] <= ram_block30a12.PORTBDATAOUT
q_b[13] <= ram_block30a13.PORTBDATAOUT
q_b[14] <= ram_block30a14.PORTBDATAOUT
q_b[15] <= ram_block30a15.PORTBDATAOUT
wren_a => ram_block30a0.PORTAWE
wren_a => ram_block30a1.PORTAWE
wren_a => ram_block30a2.PORTAWE
wren_a => ram_block30a3.PORTAWE
wren_a => ram_block30a4.PORTAWE
wren_a => ram_block30a5.PORTAWE
wren_a => ram_block30a6.PORTAWE
wren_a => ram_block30a7.PORTAWE
wren_a => ram_block30a8.PORTAWE
wren_a => ram_block30a9.PORTAWE
wren_a => ram_block30a10.PORTAWE
wren_a => ram_block30a11.PORTAWE
wren_a => ram_block30a12.PORTAWE
wren_a => ram_block30a13.PORTAWE
wren_a => ram_block30a14.PORTAWE
wren_a => ram_block30a15.PORTAWE


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe17
clock => dffpipe_2a3:dffpipe31.clock
clrn => dffpipe_2a3:dffpipe31.clrn
d[0] => dffpipe_2a3:dffpipe31.d[0]
d[1] => dffpipe_2a3:dffpipe31.d[1]
d[2] => dffpipe_2a3:dffpipe31.d[2]
d[3] => dffpipe_2a3:dffpipe31.d[3]
d[4] => dffpipe_2a3:dffpipe31.d[4]
d[5] => dffpipe_2a3:dffpipe31.d[5]
d[6] => dffpipe_2a3:dffpipe31.d[6]
d[7] => dffpipe_2a3:dffpipe31.d[7]
q[0] <= dffpipe_2a3:dffpipe31.q[0]
q[1] <= dffpipe_2a3:dffpipe31.q[1]
q[2] <= dffpipe_2a3:dffpipe31.q[2]
q[3] <= dffpipe_2a3:dffpipe31.q[3]
q[4] <= dffpipe_2a3:dffpipe31.q[4]
q[5] <= dffpipe_2a3:dffpipe31.q[5]
q[6] <= dffpipe_2a3:dffpipe31.q[6]
q[7] <= dffpipe_2a3:dffpipe31.q[7]


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe17|dffpipe_2a3:dffpipe31
clock => dffe32a[7].CLK
clock => dffe32a[6].CLK
clock => dffe32a[5].CLK
clock => dffe32a[4].CLK
clock => dffe32a[3].CLK
clock => dffe32a[2].CLK
clock => dffe32a[1].CLK
clock => dffe32a[0].CLK
clock => dffe33a[7].CLK
clock => dffe33a[6].CLK
clock => dffe33a[5].CLK
clock => dffe33a[4].CLK
clock => dffe33a[3].CLK
clock => dffe33a[2].CLK
clock => dffe33a[1].CLK
clock => dffe33a[0].CLK
clock => dffe34a[7].CLK
clock => dffe34a[6].CLK
clock => dffe34a[5].CLK
clock => dffe34a[4].CLK
clock => dffe34a[3].CLK
clock => dffe34a[2].CLK
clock => dffe34a[1].CLK
clock => dffe34a[0].CLK
clrn => dffe32a[7].ACLR
clrn => dffe32a[6].ACLR
clrn => dffe32a[5].ACLR
clrn => dffe32a[4].ACLR
clrn => dffe32a[3].ACLR
clrn => dffe32a[2].ACLR
clrn => dffe32a[1].ACLR
clrn => dffe32a[0].ACLR
clrn => dffe33a[7].ACLR
clrn => dffe33a[6].ACLR
clrn => dffe33a[5].ACLR
clrn => dffe33a[4].ACLR
clrn => dffe33a[3].ACLR
clrn => dffe33a[2].ACLR
clrn => dffe33a[1].ACLR
clrn => dffe33a[0].ACLR
clrn => dffe34a[7].ACLR
clrn => dffe34a[6].ACLR
clrn => dffe34a[5].ACLR
clrn => dffe34a[4].ACLR
clrn => dffe34a[3].ACLR
clrn => dffe34a[2].ACLR
clrn => dffe34a[1].ACLR
clrn => dffe34a[0].ACLR
q[0] <= dffe34a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe34a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe34a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe34a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe34a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe34a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe34a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe34a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24
clock => dffpipe_2a3:dffpipe31.clock
clrn => dffpipe_2a3:dffpipe31.clrn
d[0] => dffpipe_2a3:dffpipe31.d[0]
d[1] => dffpipe_2a3:dffpipe31.d[1]
d[2] => dffpipe_2a3:dffpipe31.d[2]
d[3] => dffpipe_2a3:dffpipe31.d[3]
d[4] => dffpipe_2a3:dffpipe31.d[4]
d[5] => dffpipe_2a3:dffpipe31.d[5]
d[6] => dffpipe_2a3:dffpipe31.d[6]
d[7] => dffpipe_2a3:dffpipe31.d[7]
q[0] <= dffpipe_2a3:dffpipe31.q[0]
q[1] <= dffpipe_2a3:dffpipe31.q[1]
q[2] <= dffpipe_2a3:dffpipe31.q[2]
q[3] <= dffpipe_2a3:dffpipe31.q[3]
q[4] <= dffpipe_2a3:dffpipe31.q[4]
q[5] <= dffpipe_2a3:dffpipe31.q[5]
q[6] <= dffpipe_2a3:dffpipe31.q[6]
q[7] <= dffpipe_2a3:dffpipe31.q[7]


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31
clock => dffe32a[7].CLK
clock => dffe32a[6].CLK
clock => dffe32a[5].CLK
clock => dffe32a[4].CLK
clock => dffe32a[3].CLK
clock => dffe32a[2].CLK
clock => dffe32a[1].CLK
clock => dffe32a[0].CLK
clock => dffe33a[7].CLK
clock => dffe33a[6].CLK
clock => dffe33a[5].CLK
clock => dffe33a[4].CLK
clock => dffe33a[3].CLK
clock => dffe33a[2].CLK
clock => dffe33a[1].CLK
clock => dffe33a[0].CLK
clock => dffe34a[7].CLK
clock => dffe34a[6].CLK
clock => dffe34a[5].CLK
clock => dffe34a[4].CLK
clock => dffe34a[3].CLK
clock => dffe34a[2].CLK
clock => dffe34a[1].CLK
clock => dffe34a[0].CLK
clrn => dffe32a[7].ACLR
clrn => dffe32a[6].ACLR
clrn => dffe32a[5].ACLR
clrn => dffe32a[4].ACLR
clrn => dffe32a[3].ACLR
clrn => dffe32a[2].ACLR
clrn => dffe32a[1].ACLR
clrn => dffe32a[0].ACLR
clrn => dffe33a[7].ACLR
clrn => dffe33a[6].ACLR
clrn => dffe33a[5].ACLR
clrn => dffe33a[4].ACLR
clrn => dffe33a[3].ACLR
clrn => dffe33a[2].ACLR
clrn => dffe33a[1].ACLR
clrn => dffe33a[0].ACLR
clrn => dffe34a[7].ACLR
clrn => dffe34a[6].ACLR
clrn => dffe34a[5].ACLR
clrn => dffe34a[4].ACLR
clrn => dffe34a[3].ACLR
clrn => dffe34a[2].ACLR
clrn => dffe34a[1].ACLR
clrn => dffe34a[0].ACLR
q[0] <= dffe34a[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffe34a[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffe34a[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffe34a[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffe34a[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffe34a[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffe34a[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffe34a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|add_sub_fub:add_sub12
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE