fifoasi.hier_info

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

rdclk => dffe27a[3].CLK
rdclk => dffe27a[2].CLK
rdclk => dffe27a[1].CLK
rdclk => dffe27a[0].CLK
rdclk => dffe28.CLK
rdclk => dffe29a[1].CLK
rdclk => dffe29a[0].CLK
rdempty <= pre_rdempty.DB_MAX_OUTPUT_PORT_TYPE
rdfull <= dffe28.DB_MAX_OUTPUT_PORT_TYPE
rdreq => scfifo:scfifo14.rdreq
rdreq => valid_rreq.IN0
rdusedw[0] <= dffe27a[0].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[1] <= dffe27a[1].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[2] <= dffe27a[2].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[3] <= dffe27a[3].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[4] <= dffe27a[4].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[5] <= dffe27a[5].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[6] <= dffe27a[6].DB_MAX_OUTPUT_PORT_TYPE
rdusedw[7] <= dffe27a[7].DB_MAX_OUTPUT_PORT_TYPE
wrclk => a_graycounter_i06:a_graycounter2.clock
wrclk => altsyncram_bv01:altsyncram1.clock0
wrclk => alt_synch_pipe_2a3:alt_synch_pipe17.clock
wrclk => cntr_uu7:cntr4.clock
wrclk => dffe16a[7].CLK
wrclk => dffe16a[6].CLK
wrclk => dffe16a[5].CLK
wrclk => dffe16a[4].CLK
wrclk => dffe16a[3].CLK
wrclk => dffe16a[2].CLK
wrclk => dffe16a[1].CLK
wrclk => dffe16a[0].CLK
wrclk => dffe18a[7].CLK
wrclk => dffe18a[6].CLK
wrclk => dffe18a[5].CLK
wrclk => dffe18a[4].CLK
wrclk => dffe18a[3].CLK
wrclk => dffe18a[2].CLK
wrclk => dffe18a[1].CLK
wrclk => dffe18a[0].CLK
wrclk => dffe19a[7].CLK
wrclk => dffe19a[6].CLK
wrclk => dffe19a[5].CLK
wrclk => dffe19a[4].CLK
wrclk => dffe19a[3].CLK
wrclk => dffe19a[2].CLK
wrclk => dffe19a[1].CLK
wrclk => dffe19a[0].CLK
wrclk => dffe20a[7].CLK
wrclk => dffe20a[6].CLK
wrclk => dffe20a[5].CLK
wrclk => dffe20a[4].CLK
wrclk => dffe20a[3].CLK
wrclk => dffe20a[2].CLK
wrclk => dffe20a[1].CLK
wrclk => dffe20a[0].CLK
wrclk => dffe21.CLK
wrclk => dffe22.CLK
wrclk => dffe23.CLK
wrfull <= dffe23.DB_MAX_OUTPUT_PORT_TYPE
wrreq => valid_wrreq.IN1
wrreq => dffe21.DATAIN
wrusedw[0] <= dffe20a[0].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[1] <= dffe20a[1].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[2] <= dffe20a[2].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[3] <= dffe20a[3].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[4] <= dffe20a[4].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[5] <= dffe20a[5].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[6] <= dffe20a[6].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[7] <= dffe20a[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_gray2bin_p4b:a_gray2bin11
bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
bin[7] <= gray[7].DB_MAX_OUTPUT_PORT_TYPE
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN0
gray[6] => xor6.IN1
gray[7] => bin[7].DATAIN
gray[7] => xor6.IN0


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_gray2bin_p4b:a_gray2bin3
bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
bin[7] <= gray[7].DB_MAX_OUTPUT_PORT_TYPE
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN0
gray[6] => xor6.IN1
gray[7] => bin[7].DATAIN
gray[7] => xor6.IN0


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter2
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => parity.ACLR
clk_en => countera0.ENA
clk_en => countera1.ENA
clk_en => countera2.ENA
clk_en => countera3.ENA
clk_en => countera4.ENA
clk_en => countera5.ENA
clk_en => countera6.ENA
clk_en => countera7.ENA
clk_en => parity.ENA
clock => countera0.CLK
clock => countera1.CLK
clock => countera2.CLK
clock => countera3.CLK
clock => countera4.CLK
clock => countera5.CLK
clock => countera6.CLK
clock => countera7.CLK
clock => parity.CLK
q[0] <= countera0.REGOUT
q[1] <= countera1.REGOUT
q[2] <= countera2.REGOUT
q[3] <= countera3.REGOUT
q[4] <= countera4.REGOUT
q[5] <= countera5.REGOUT
q[6] <= countera6.REGOUT
q[7] <= countera7.REGOUT


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => parity.ACLR
clk_en => countera0.ENA
clk_en => countera1.ENA
clk_en => countera2.ENA
clk_en => countera3.ENA
clk_en => countera4.ENA
clk_en => countera5.ENA
clk_en => countera6.ENA
clk_en => countera7.ENA
clk_en => parity.ENA
clock => countera0.CLK
clock => countera1.CLK
clock => countera2.CLK
clock => countera3.CLK
clock => countera4.CLK
clock => countera5.CLK
clock => countera6.CLK
clock => countera7.CLK
clock => parity.CLK
q[0] <= countera0.REGOUT
q[1] <= countera1.REGOUT
q[2] <= countera2.REGOUT
q[3] <= countera3.REGOUT
q[4] <= countera4.REGOUT
q[5] <= countera5.REGOUT
q[6] <= countera6.REGOUT
q[7] <= countera7.REGOUT


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter9
aclr => countera0.ACLR
aclr => countera1.ACLR
aclr => countera2.ACLR
aclr => countera3.ACLR
aclr => countera4.ACLR
aclr => countera5.ACLR
aclr => countera6.ACLR
aclr => countera7.ACLR
aclr => parity.ACLR
clk_en => countera0.ENA
clk_en => countera1.ENA
clk_en => countera2.ENA
clk_en => countera3.ENA
clk_en => countera4.ENA
clk_en => countera5.ENA
clk_en => countera6.ENA
clk_en => countera7.ENA
clk_en => parity.ENA
clock => countera0.CLK
clock => countera1.CLK
clock => countera2.CLK
clock => countera3.CLK
clock => countera4.CLK
clock => countera5.CLK
clock => countera6.CLK
clock => countera7.CLK
clock => parity.CLK
q[0] <= countera0.REGOUT
q[1] <= countera1.REGOUT
q[2] <= countera2.REGOUT
q[3] <= countera3.REGOUT
q[4] <= countera4.REGOUT
q[5] <= countera5.REGOUT
q[6] <= countera6.REGOUT
q[7] <= countera7.REGOUT


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|altsyncram_bv01:altsyncram1
address_a[0] => ram_block30a0.PORTAADDR
address_a[0] => ram_block30a1.PORTAADDR
address_a[0] => ram_block30a2.PORTAADDR
address_a[0] => ram_block30a3.PORTAADDR
address_a[0] => ram_block30a4.PORTAADDR
address_a[0] => ram_block30a5.PORTAADDR
address_a[0] => ram_block30a6.PORTAADDR
address_a[0] => ram_block30a7.PORTAADDR
address_a[0] => ram_block30a8.PORTAADDR
address_a[0] => ram_block30a9.PORTAADDR
address_a[0] => ram_block30a10.PORTAADDR
address_a[0] => ram_block30a11.PORTAADDR
address_a[0] => ram_block30a12.PORTAADDR
address_a[0] => ram_block30a13.PORTAADDR
address_a[0] => ram_block30a14.PORTAADDR
address_a[0] => ram_block30a15.PORTAADDR
address_a[1] => ram_block30a0.PORTAADDR1
address_a[1] => ram_block30a1.PORTAADDR1
address_a[1] => ram_block30a2.PORTAADDR1
address_a[1] => ram_block30a3.PORTAADDR1
address_a[1] => ram_block30a4.PORTAADDR1
address_a[1] => ram_block30a5.PORTAADDR1
address_a[1] => ram_block30a6.PORTAADDR1
address_a[1] => ram_block30a7.PORTAADDR1
address_a[1] => ram_block30a8.PORTAADDR1
address_a[1] => ram_block30a9.PORTAADDR1
address_a[1] => ram_block30a10.PORTAADDR1
address_a[1] => ram_block30a11.PORTAADDR1
address_a[1] => ram_block30a12.PORTAADDR1
address_a[1] => ram_block30a13.PORTAADDR1
address_a[1] => ram_block30a14.PORTAADDR1
address_a[1] => ram_block30a15.PORTAADDR1
address_a[2] => ram_block30a0.PORTAADDR2
address_a[2] => ram_block30a1.PORTAADDR2
address_a[2] => ram_block30a2.PORTAADDR2
address_a[2] => ram_block30a3.PORTAADDR2
address_a[2] => ram_block30a4.PORTAADDR2
address_a[2] => ram_block30a5.PORTAADDR2
address_a[2] => ram_block30a6.PORTAADDR2
address_a[2] => ram_block30a7.PORTAADDR2
address_a[2] => ram_block30a8.PORTAADDR2
address_a[2] => ram_block30a9.PORTAADDR2
address_a[2] => ram_block30a10.PORTAADDR2
address_a[2] => ram_block30a11.PORTAADDR2
address_a[2] => ram_block30a12.PORTAADDR2
address_a[2] => ram_block30a13.PORTAADDR2
address_a[2] => ram_block30a14.PORTAADDR2
address_a[2] => ram_block30a15.PORTAADDR2
address_a[3] => ram_block30a0.PORTAADDR3
address_a[3] => ram_block30a1.PORTAADDR3
address_a[3] => ram_block30a2.PORTAADDR3
address_a[3] => ram_block30a3.PORTAADDR3
address_a[3] => ram_block30a4.PORTAADDR3
address_a[3] => ram_block30a5.PORTAADDR3
address_a[3] => ram_block30a6.PORTAADDR3
address_a[3] => ram_block30a7.PORTAADDR3
address_a[3] => ram_block30a8.PORTAADDR3
address_a[3] => ram_block30a9.PORTAADDR3
address_a[3] => ram_block30a10.PORTAADDR3
address_a[3] => ram_block30a11.PORTAADDR3
address_a[3] => ram_block30a12.PORTAADDR3
address_a[3] => ram_block30a13.PORTAADDR3
address_a[3] => ram_block30a14.PORTAADDR3
address_a[3] => ram_block30a15.PORTAADDR3
address_a[4] => ram_block30a0.PORTAADDR4
address_a[4] => ram_block30a1.PORTAADDR4
address_a[4] => ram_block30a2.PORTAADDR4
address_a[4] => ram_block30a3.PORTAADDR4
address_a[4] => ram_block30a4.PORTAADDR4
address_a[4] => ram_block30a5.PORTAADDR4
address_a[4] => ram_block30a6.PORTAADDR4
address_a[4] => ram_block30a7.PORTAADDR4
address_a[4] => ram_block30a8.PORTAADDR4
address_a[4] => ram_block30a9.PORTAADDR4
address_a[4] => ram_block30a10.PORTAADDR4
address_a[4] => ram_block30a11.PORTAADDR4
address_a[4] => ram_block30a12.PORTAADDR4
address_a[4] => ram_block30a13.PORTAADDR4
address_a[4] => ram_block30a14.PORTAADDR4
address_a[4] => ram_block30a15.PORTAADDR4
address_a[5] => ram_block30a0.PORTAADDR5
address_a[5] => ram_block30a1.PORTAADDR5
address_a[5] => ram_block30a2.PORTAADDR5
address_a[5] => ram_block30a3.PORTAADDR5
address_a[5] => ram_block30a4.PORTAADDR5
address_a[5] => ram_block30a5.PORTAADDR5
address_a[5] => ram_block30a6.PORTAADDR5
address_a[5] => ram_block30a7.PORTAADDR5
address_a[5] => ram_block30a8.PORTAADDR5
address_a[5] => ram_block30a9.PORTAADDR5
address_a[5] => ram_block30a10.PORTAADDR5
address_a[5] => ram_block30a11.PORTAADDR5
address_a[5] => ram_block30a12.PORTAADDR5
address_a[5] => ram_block30a13.PORTAADDR5
address_a[5] => ram_block30a14.PORTAADDR5
address_a[5] => ram_block30a15.PORTAADDR5
address_a[6] => ram_block30a0.PORTAADDR6
address_a[6] => ram_block30a1.PORTAADDR6
address_a[6] => ram_block30a2.PORTAADDR6
address_a[6] => ram_block30a3.PORTAADDR6
address_a[6] => ram_block30a4.PORTAADDR6
address_a[6] => ram_block30a5.PORTAADDR6
address_a[6] => ram_block30a6.PORTAADDR6
address_a[6] => ram_block30a7.PORTAADDR6
address_a[6] => ram_block30a8.PORTAADDR6
address_a[6] => ram_block30a9.PORTAADDR6
address_a[6] => ram_block30a10.PORTAADDR6
address_a[6] => ram_block30a11.PORTAADDR6
address_a[6] => ram_block30a12.PORTAADDR6
address_a[6] => ram_block30a13.PORTAADDR6
address_a[6] => ram_block30a14.PORTAADDR6
address_a[6] => ram_block30a15.PORTAADDR6
address_a[7] => ram_block30a0.PORTAADDR7
address_a[7] => ram_block30a1.PORTAADDR7
address_a[7] => ram_block30a2.PORTAADDR7
address_a[7] => ram_block30a3.PORTAADDR7
address_a[7] => ram_block30a4.PORTAADDR7
address_a[7] => ram_block30a5.PORTAADDR7
address_a[7] => ram_block30a6.PORTAADDR7
address_a[7] => ram_block30a7.PORTAADDR7
address_a[7] => ram_block30a8.PORTAADDR7
address_a[7] => ram_block30a9.PORTAADDR7
address_a[7] => ram_block30a10.PORTAADDR7
address_a[7] => ram_block30a11.PORTAADDR7
address_a[7] => ram_block30a12.PORTAADDR7
address_a[7] => ram_block30a13.PORTAADDR7
address_a[7] => ram_block30a14.PORTAADDR7
address_a[7] => ram_block30a15.PORTAADDR7
address_b[0] => ram_block30a0.PORTBADDR
address_b[0] => ram_block30a1.PORTBADDR
address_b[0] => ram_block30a2.PORTBADDR
address_b[0] => ram_block30a3.PORTBADDR
address_b[0] => ram_block30a4.PORTBADDR
address_b[0] => ram_block30a5.PORTBADDR
address_b[0] => ram_block30a6.PORTBADDR
address_b[0] => ram_block30a7.PORTBADDR
address_b[0] => ram_block30a8.PORTBADDR
address_b[0] => ram_block30a9.PORTBADDR
address_b[0] => ram_block30a10.PORTBADDR
address_b[0] => ram_block30a11.PORTBADDR
address_b[0] => ram_block30a12.PORTBADDR
address_b[0] => ram_block30a13.PORTBADDR
address_b[0] => ram_block30a14.PORTBADDR
address_b[0] => ram_block30a15.PORTBADDR
address_b[1] => ram_block30a0.PORTBADDR1