fifoasi.hier_info

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

|fifo_asi
INTA <= INT:inst23.INT
RXSTA0 => inst5.IN0
RXSTA1 => inst5.IN1
RXSTA2 => inst5.IN2
SYS_RST => 8to16ddf:inst29.CLR
SYS_RST => 8to16ddf:inst30.CLR
SYS_RST => asitodsp:inst.aclr
SYS_RST => 8to16ddf:inst31.CLR
SYS_RST => asitodsp:inst12.aclr
SYS_RST => 8to16ddf:inst32.CLR
SYS_RST => asitodsp:inst13.aclr
SYS_RST => asitodsp:inst11.aclr
SYS_RST => dsptoasi:inst39.aclr
SYS_RST => 16to8ddf:inst28.aclr
SYS_RST => dsptoasi:inst38.aclr
SYS_RST => 16to8ddf:inst25.aclr
SYS_RST => dsptoasi:inst40.aclr
SYS_RST => 16to8ddf:inst22.aclr
SYS_RST => dsptoasi:inst41.aclr
SYS_RST => 16to8ddf:inst21.aclr
SYS_RST => TRSTZ.DATAIN
SYS_RST => lpm_dff2:inst54.aclr
SYS_RST => lpm_dff8:inst19.aclr
ASICLK => altpll0:inst17.inclk0
RXDA[0] => 8to16ddf:inst29.OUTASI[0]
RXDA[1] => 8to16ddf:inst29.OUTASI[1]
RXDA[2] => 8to16ddf:inst29.OUTASI[2]
RXDA[3] => 8to16ddf:inst29.OUTASI[3]
RXDA[4] => 8to16ddf:inst29.OUTASI[4]
RXDA[5] => 8to16ddf:inst29.OUTASI[5]
RXDA[6] => 8to16ddf:inst29.OUTASI[6]
RXDA[7] => 8to16ddf:inst29.OUTASI[7]
SOE3 => uncode:inst36.SOE3
BE0 => uncode:inst36.BE0
CE[0] => uncode:inst36.CE[0]
CE[1] => uncode:inst36.CE[1]
CE[2] => uncode:inst36.CE[2]
CE[3] => uncode:inst36.CE[3]
dspio[0] <= uncode:inst36.DSPIO[0]
dspio[1] <= uncode:inst36.DSPIO[1]
dspio[2] <= uncode:inst36.DSPIO[2]
dspio[3] <= uncode:inst36.DSPIO[3]
dspio[4] <= uncode:inst36.DSPIO[4]
dspio[5] <= uncode:inst36.DSPIO[5]
dspio[6] <= uncode:inst36.DSPIO[6]
dspio[7] <= uncode:inst36.DSPIO[7]
dspio[8] <= uncode:inst36.DSPIO[8]
dspio[9] <= uncode:inst36.DSPIO[9]
dspio[10] <= uncode:inst36.DSPIO[10]
dspio[11] <= uncode:inst36.DSPIO[11]
dspio[12] <= uncode:inst36.DSPIO[12]
dspio[13] <= uncode:inst36.DSPIO[13]
dspio[14] <= uncode:inst36.DSPIO[14]
dspio[15] <= uncode:inst36.DSPIO[15]
EA[0] => uncode:inst36.EA[0]
EA[1] => uncode:inst36.EA[1]
EA[2] => uncode:inst36.EA[2]
EA[3] => uncode:inst36.EA[3]
EA[4] => uncode:inst36.EA[4]
EA[5] => uncode:inst36.EA[5]
EA[6] => uncode:inst36.EA[6]
EA[7] => uncode:inst36.EA[7]
EA[8] => uncode:inst36.EA[8]
EA[9] => uncode:inst36.EA[9]
LFI[0] => uncode:inst36.LFI[0]
LFI[0] => lpm_dff8:inst19.data[0]
LFI[0] => lpm_bustri7:inst20.tridata[0]
LFI[1] => uncode:inst36.LFI[1]
LFI[1] => lpm_dff8:inst19.data[1]
LFI[1] => lpm_bustri7:inst20.tridata[1]
LFI[2] => uncode:inst36.LFI[2]
LFI[2] => lpm_dff8:inst19.data[2]
LFI[2] => lpm_bustri7:inst20.tridata[2]
LFI[3] => uncode:inst36.LFI[3]
LFI[3] => lpm_dff8:inst19.data[3]
LFI[3] => lpm_bustri7:inst20.tridata[3]
RXSTB0 => inst6.IN0
RXSTB1 => inst6.IN1
RXSTB2 => inst6.IN2
RXDB[0] => 8to16ddf:inst30.OUTASI[0]
RXDB[1] => 8to16ddf:inst30.OUTASI[1]
RXDB[2] => 8to16ddf:inst30.OUTASI[2]
RXDB[3] => 8to16ddf:inst30.OUTASI[3]
RXDB[4] => 8to16ddf:inst30.OUTASI[4]
RXDB[5] => 8to16ddf:inst30.OUTASI[5]
RXDB[6] => 8to16ddf:inst30.OUTASI[6]
RXDB[7] => 8to16ddf:inst30.OUTASI[7]
DSPCLK => altpll1:inst18.inclk0
RXSTC0 => inst7.IN0
RXSTC1 => inst7.IN1
RXSTC2 => inst7.IN2
RXDC[0] => 8to16ddf:inst31.OUTASI[0]
RXDC[1] => 8to16ddf:inst31.OUTASI[1]
RXDC[2] => 8to16ddf:inst31.OUTASI[2]
RXDC[3] => 8to16ddf:inst31.OUTASI[3]
RXDC[4] => 8to16ddf:inst31.OUTASI[4]
RXDC[5] => 8to16ddf:inst31.OUTASI[5]
RXDC[6] => 8to16ddf:inst31.OUTASI[6]
RXDC[7] => 8to16ddf:inst31.OUTASI[7]
RXSTD0 => inst8.IN0
RXSTD1 => inst8.IN1
RXSTD2 => inst8.IN2
RXDD[0] => 8to16ddf:inst32.OUTASI[0]
RXDD[1] => 8to16ddf:inst32.OUTASI[1]
RXDD[2] => 8to16ddf:inst32.OUTASI[2]
RXDD[3] => 8to16ddf:inst32.OUTASI[3]
RXDD[4] => 8to16ddf:inst32.OUTASI[4]
RXDD[5] => 8to16ddf:inst32.OUTASI[5]
RXDD[6] => 8to16ddf:inst32.OUTASI[6]
RXDD[7] => 8to16ddf:inst32.OUTASI[7]
INTC <= INT:inst26.INT
INTD <= INT:inst27.INT
INTB <= INT:inst24.INT
TXCTD0 <= 16to8ddf:inst28.rempty
TXCTC0 <= 16to8ddf:inst25.rempty
TXCTB0 <= 16to8ddf:inst22.rempty
TXCTA0 <= 16to8ddf:inst21.rempty
LPEN <= control:inst15.LPEN
SDASEL <= control:inst15.SDASEL
DECMODE <= control:inst15.DECMODE
BISTLE <= control:inst15.BISTLE
RXLE <= control:inst15.RXLE
OELE <= control:inst15.OELE
SCSEL <= control:inst15.SCSEL
RXMODE0 <= control:inst15.RXMODE0
RXMODE1 <= control:inst15.RXMODE1
TXMODE0 <= control:inst15.TXMODE0
TXMODE1 <= control:inst15.TXMODE1
BOND_INH <= control:inst15.BOND_INH
TXRST <= control:inst15.TXRST
TRSTZ <= SYS_RST.DB_MAX_OUTPUT_PORT_TYPE
OUTIO[0] <= lpm_dff2:inst54.q[0]
OUTIO[1] <= lpm_dff2:inst54.q[1]
OUTIO[2] <= lpm_dff2:inst54.q[2]
OUTIO[3] <= lpm_dff2:inst54.q[3]
OUTIO[4] <= lpm_dff2:inst54.q[4]
OUTIO[5] <= lpm_dff2:inst54.q[5]
OUTIO[6] <= lpm_dff2:inst54.q[6]
OUTIO[7] <= lpm_dff2:inst54.q[7]
OUTIO[8] <= lpm_dff2:inst54.q[8]
OUTIO[9] <= lpm_dff2:inst54.q[9]
OUTIO[10] <= lpm_dff2:inst54.q[10]
OUTIO[11] <= lpm_dff2:inst54.q[11]
OUTIO[12] <= lpm_dff2:inst54.q[12]
OUTIO[13] <= lpm_dff2:inst54.q[13]
OUTIO[14] <= lpm_dff2:inst54.q[14]
OUTIO[15] <= lpm_dff2:inst54.q[15]
TXCTABCD[3] <= lpm_constant0:inst14.result[0]
TXCTABCD[2] <= lpm_constant0:inst14.result[1]
TXCTABCD[1] <= lpm_constant0:inst14.result[2]
TXCTABCD[0] <= lpm_constant0:inst14.result[3]
TXDA[0] <= 16to8ddf:inst21.rq[0]
TXDA[1] <= 16to8ddf:inst21.rq[1]
TXDA[2] <= 16to8ddf:inst21.rq[2]
TXDA[3] <= 16to8ddf:inst21.rq[3]
TXDA[4] <= 16to8ddf:inst21.rq[4]
TXDA[5] <= 16to8ddf:inst21.rq[5]
TXDA[6] <= 16to8ddf:inst21.rq[6]
TXDA[7] <= 16to8ddf:inst21.rq[7]
TXDB[0] <= 16to8ddf:inst22.rq[0]
TXDB[1] <= 16to8ddf:inst22.rq[1]
TXDB[2] <= 16to8ddf:inst22.rq[2]
TXDB[3] <= 16to8ddf:inst22.rq[3]
TXDB[4] <= 16to8ddf:inst22.rq[4]
TXDB[5] <= 16to8ddf:inst22.rq[5]
TXDB[6] <= 16to8ddf:inst22.rq[6]
TXDB[7] <= 16to8ddf:inst22.rq[7]
TXDC[0] <= 16to8ddf:inst25.rq[0]
TXDC[1] <= 16to8ddf:inst25.rq[1]
TXDC[2] <= 16to8ddf:inst25.rq[2]
TXDC[3] <= 16to8ddf:inst25.rq[3]
TXDC[4] <= 16to8ddf:inst25.rq[4]
TXDC[5] <= 16to8ddf:inst25.rq[5]
TXDC[6] <= 16to8ddf:inst25.rq[6]
TXDC[7] <= 16to8ddf:inst25.rq[7]
TXDD[0] <= 16to8ddf:inst28.rq[0]
TXDD[1] <= 16to8ddf:inst28.rq[1]
TXDD[2] <= 16to8ddf:inst28.rq[2]
TXDD[3] <= 16to8ddf:inst28.rq[3]
TXDD[4] <= 16to8ddf:inst28.rq[4]
TXDD[5] <= 16to8ddf:inst28.rq[5]
TXDD[6] <= 16to8ddf:inst28.rq[6]
TXDD[7] <= 16to8ddf:inst28.rq[7]


|fifo_asi|INT:inst23
WRUSEDW[0] => ~NO_FANOUT~
WRUSEDW[1] => ~NO_FANOUT~
WRUSEDW[2] => ~NO_FANOUT~
WRUSEDW[3] => ~NO_FANOUT~
WRUSEDW[4] => ~NO_FANOUT~
WRUSEDW[5] => ~NO_FANOUT~
WRUSEDW[6] => ~NO_FANOUT~
WRUSEDW[7] => INT.DATAIN
INT <= WRUSEDW[7].DB_MAX_OUTPUT_PORT_TYPE


|fifo_asi|asitodsp:inst11
data[0] => data[0]~15.IN1
data[1] => data[1]~14.IN1
data[2] => data[2]~13.IN1
data[3] => data[3]~12.IN1
data[4] => data[4]~11.IN1
data[5] => data[5]~10.IN1
data[6] => data[6]~9.IN1
data[7] => data[7]~8.IN1
data[8] => data[8]~7.IN1
data[9] => data[9]~6.IN1
data[10] => data[10]~5.IN1
data[11] => data[11]~4.IN1
data[12] => data[12]~3.IN1
data[13] => data[13]~2.IN1
data[14] => data[14]~1.IN1
data[15] => data[15]~0.IN1
wrreq => wrreq~0.IN1
rdreq => rdreq~0.IN1
rdclk => rdclk~0.IN1
wrclk => wrclk~0.IN1
aclr => aclr~0.IN1
q[0] <= dcfifo:dcfifo_component.q
q[1] <= dcfifo:dcfifo_component.q
q[2] <= dcfifo:dcfifo_component.q
q[3] <= dcfifo:dcfifo_component.q
q[4] <= dcfifo:dcfifo_component.q
q[5] <= dcfifo:dcfifo_component.q
q[6] <= dcfifo:dcfifo_component.q
q[7] <= dcfifo:dcfifo_component.q
q[8] <= dcfifo:dcfifo_component.q
q[9] <= dcfifo:dcfifo_component.q
q[10] <= dcfifo:dcfifo_component.q
q[11] <= dcfifo:dcfifo_component.q
q[12] <= dcfifo:dcfifo_component.q
q[13] <= dcfifo:dcfifo_component.q
q[14] <= dcfifo:dcfifo_component.q
q[15] <= dcfifo:dcfifo_component.q
wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
wrusedw[7] <= dcfifo:dcfifo_component.wrusedw


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component
data[0] => dcfifo_dv21:auto_generated.data[0]
data[1] => dcfifo_dv21:auto_generated.data[1]
data[2] => dcfifo_dv21:auto_generated.data[2]
data[3] => dcfifo_dv21:auto_generated.data[3]
data[4] => dcfifo_dv21:auto_generated.data[4]
data[5] => dcfifo_dv21:auto_generated.data[5]
data[6] => dcfifo_dv21:auto_generated.data[6]
data[7] => dcfifo_dv21:auto_generated.data[7]
data[8] => dcfifo_dv21:auto_generated.data[8]
data[9] => dcfifo_dv21:auto_generated.data[9]
data[10] => dcfifo_dv21:auto_generated.data[10]
data[11] => dcfifo_dv21:auto_generated.data[11]
data[12] => dcfifo_dv21:auto_generated.data[12]
data[13] => dcfifo_dv21:auto_generated.data[13]
data[14] => dcfifo_dv21:auto_generated.data[14]
data[15] => dcfifo_dv21:auto_generated.data[15]
q[0] <= dcfifo_dv21:auto_generated.q[0]
q[1] <= dcfifo_dv21:auto_generated.q[1]
q[2] <= dcfifo_dv21:auto_generated.q[2]
q[3] <= dcfifo_dv21:auto_generated.q[3]
q[4] <= dcfifo_dv21:auto_generated.q[4]
q[5] <= dcfifo_dv21:auto_generated.q[5]
q[6] <= dcfifo_dv21:auto_generated.q[6]
q[7] <= dcfifo_dv21:auto_generated.q[7]
q[8] <= dcfifo_dv21:auto_generated.q[8]
q[9] <= dcfifo_dv21:auto_generated.q[9]
q[10] <= dcfifo_dv21:auto_generated.q[10]
q[11] <= dcfifo_dv21:auto_generated.q[11]
q[12] <= dcfifo_dv21:auto_generated.q[12]
q[13] <= dcfifo_dv21:auto_generated.q[13]
q[14] <= dcfifo_dv21:auto_generated.q[14]
q[15] <= dcfifo_dv21:auto_generated.q[15]
rdclk => dcfifo_dv21:auto_generated.rdclk
rdreq => dcfifo_dv21:auto_generated.rdreq
wrclk => dcfifo_dv21:auto_generated.wrclk
wrreq => dcfifo_dv21:auto_generated.wrreq
aclr => dcfifo_dv21:auto_generated.aclr
rdempty <= <UNC>
rdfull <= <UNC>
wrempty <= <UNC>
wrfull <= <UNC>
rdusedw[0] <= <UNC>
rdusedw[1] <= <UNC>
rdusedw[2] <= <UNC>
rdusedw[3] <= <UNC>
rdusedw[4] <= <UNC>
rdusedw[5] <= <UNC>
rdusedw[6] <= <UNC>
rdusedw[7] <= <UNC>
wrusedw[0] <= dcfifo_dv21:auto_generated.wrusedw[0]
wrusedw[1] <= dcfifo_dv21:auto_generated.wrusedw[1]
wrusedw[2] <= dcfifo_dv21:auto_generated.wrusedw[2]
wrusedw[3] <= dcfifo_dv21:auto_generated.wrusedw[3]
wrusedw[4] <= dcfifo_dv21:auto_generated.wrusedw[4]
wrusedw[5] <= dcfifo_dv21:auto_generated.wrusedw[5]
wrusedw[6] <= dcfifo_dv21:auto_generated.wrusedw[6]
wrusedw[7] <= dcfifo_dv21:auto_generated.wrusedw[7]


|fifo_asi|asitodsp:inst11|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated
aclr => a_graycounter_i06:a_graycounter2.aclr
aclr => a_graycounter_i06:a_graycounter8.aclr
aclr => a_graycounter_i06:a_graycounter9.aclr
aclr => cntr_uu7:cntr10.aclr
aclr => cntr_uu7:cntr4.aclr
aclr => scfifo:scfifo14.aclr
data[0] => altsyncram_bv01:altsyncram1.data_a[0]
data[1] => altsyncram_bv01:altsyncram1.data_a[1]
data[2] => altsyncram_bv01:altsyncram1.data_a[2]
data[3] => altsyncram_bv01:altsyncram1.data_a[3]
data[4] => altsyncram_bv01:altsyncram1.data_a[4]
data[5] => altsyncram_bv01:altsyncram1.data_a[5]
data[6] => altsyncram_bv01:altsyncram1.data_a[6]
data[7] => altsyncram_bv01:altsyncram1.data_a[7]
data[8] => altsyncram_bv01:altsyncram1.data_a[8]
data[9] => altsyncram_bv01:altsyncram1.data_a[9]
data[10] => altsyncram_bv01:altsyncram1.data_a[10]
data[11] => altsyncram_bv01:altsyncram1.data_a[11]
data[12] => altsyncram_bv01:altsyncram1.data_a[12]
data[13] => altsyncram_bv01:altsyncram1.data_a[13]
data[14] => altsyncram_bv01:altsyncram1.data_a[14]
data[15] => altsyncram_bv01:altsyncram1.data_a[15]
q[0] <= scfifo:scfifo14.q[0]
q[1] <= scfifo:scfifo14.q[1]
q[2] <= scfifo:scfifo14.q[2]
q[3] <= scfifo:scfifo14.q[3]
q[4] <= scfifo:scfifo14.q[4]
q[5] <= scfifo:scfifo14.q[5]
q[6] <= scfifo:scfifo14.q[6]
q[7] <= scfifo:scfifo14.q[7]
q[8] <= scfifo:scfifo14.q[8]
q[9] <= scfifo:scfifo14.q[9]
q[10] <= scfifo:scfifo14.q[10]
q[11] <= scfifo:scfifo14.q[11]
q[12] <= scfifo:scfifo14.q[12]
q[13] <= scfifo:scfifo14.q[13]
q[14] <= scfifo:scfifo14.q[14]
q[15] <= scfifo:scfifo14.q[15]
rdclk => a_graycounter_i06:a_graycounter8.clock
rdclk => a_graycounter_i06:a_graycounter9.clock
rdclk => altsyncram_bv01:altsyncram1.clock1
rdclk => alt_synch_pipe_2a3:alt_synch_pipe24.clock
rdclk => cntr_uu7:cntr10.clock
rdclk => scfifo:scfifo14.clock
rdclk => dffe25a[7].CLK
rdclk => dffe25a[6].CLK
rdclk => dffe25a[5].CLK
rdclk => dffe25a[4].CLK
rdclk => dffe25a[3].CLK
rdclk => dffe25a[2].CLK
rdclk => dffe25a[1].CLK
rdclk => dffe25a[0].CLK
rdclk => dffe26a[7].CLK
rdclk => dffe26a[6].CLK
rdclk => dffe26a[5].CLK
rdclk => dffe26a[4].CLK
rdclk => dffe26a[3].CLK
rdclk => dffe26a[2].CLK
rdclk => dffe26a[1].CLK
rdclk => dffe26a[0].CLK
rdclk => dffe27a[7].CLK
rdclk => dffe27a[6].CLK
rdclk => dffe27a[5].CLK
rdclk => dffe27a[4].CLK