📄 dcfifo_dv21.tdf
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--dcfifo ADD_RAM_OUTPUT_REGISTER="ON" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTHU=8 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdreq wrclk wrreq wrusedw lpm_hint="RAM_BLOCK_TYPE=M4K" RAM_BLOCK_TYPE="M4K"
--VERSION_BEGIN 4.1 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:03:05:02:46:42:SJ cbx_altdpram 2004:05:14:13:10:08:SJ cbx_altsyncram 2004:06:23:18:19:30:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_dcfifo 2004:06:03:11:08:42:SJ cbx_fifo_common 2003:08:19:18:07:00:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 2004:04:12:17:30:12:SJ cbx_lpm_counter 2004:04:21:01:21:20:SJ cbx_lpm_decode 2004:03:10:10:44:06:SJ cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_scfifo 2004:06:03:11:12:32:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ cbx_util 2004:03:29:17:03:30:SJ VERSION_END
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
FUNCTION a_gray2bin_p4b (gray[7..0])
RETURNS ( bin[7..0]);
FUNCTION a_graycounter_i06 (aclr, clk_en, clock)
RETURNS ( q[7..0]);
FUNCTION altsyncram_bv01 (address_a[7..0], address_b[7..0], clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION alt_synch_pipe_2a3 (clock, clrn, d[7..0])
RETURNS ( q[7..0]);
FUNCTION add_sub_fub (dataa[7..0], datab[7..0])
RETURNS ( result[7..0]);
FUNCTION cntr_uu7 (aclr, clk_en, clock)
RETURNS ( cout, q[7..0]);
FUNCTION scfifo (aclr, clock, data[lpm_width-1..0], rdreq, sclr, wrreq)
WITH ( ALLOW_RWCYCLE_WHEN_FULL, ALMOST_EMPTY_VALUE, ALMOST_FULL_VALUE, LPM_NUMWORDS, LPM_SHOWAHEAD, lpm_width, lpm_widthu, OVERFLOW_CHECKING, UNDERFLOW_CHECKING, USE_EAB)
RETURNS ( almost_empty, almost_full, empty, full, q[lpm_width-1..0], usedw[lpm_widthu-1..0]);
--synthesis_resources = lut 143 ram_bits (M4K) 4096 scfifo 1
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
SUBDESIGN dcfifo_dv21
(
aclr : input;
data[15..0] : input;
q[15..0] : output;
rdclk : input;
rdempty : output;
rdfull : output;
rdreq : input;
rdusedw[7..0] : output;
wrclk : input;
wrempty : output;
wrfull : output;
wrreq : input;
wrusedw[7..0] : output;
)
VARIABLE
a_gray2bin11 : a_gray2bin_p4b;
a_gray2bin3 : a_gray2bin_p4b;
a_graycounter2 : a_graycounter_i06;
a_graycounter8 : a_graycounter_i06;
a_graycounter9 : a_graycounter_i06;
altsyncram1 : altsyncram_bv01;
dffe16a[7..0] : dffe;
dffe18a[7..0] : dffe;
dffe19a[7..0] : dffe;
dffe20a[7..0] : dffe;
dffe21 : dffe;
dffe22 : dffe;
dffe23 : dffe;
dffe25a[7..0] : dffe;
dffe26a[7..0] : dffe;
dffe27a[7..0] : dffe;
dffe28 : dffe;
dffe29a[1..0] : dffe;
alt_synch_pipe17 : alt_synch_pipe_2a3;
alt_synch_pipe24 : alt_synch_pipe_2a3;
add_sub12 : add_sub_fub;
add_sub5 : add_sub_fub;
cmpr13_aeb_int : WIRE;
cmpr13_agb_int : WIRE;
cmpr13_ageb : WIRE;
cmpr13_dataa[7..0] : WIRE;
cmpr13_datab[7..0] : WIRE;
cmpr15_aeb_int : WIRE;
cmpr15_aeb : WIRE;
cmpr15_dataa[7..0] : WIRE;
cmpr15_datab[7..0] : WIRE;
cmpr6_aeb_int : WIRE;
cmpr6_agb_int : WIRE;
cmpr6_ageb : WIRE;
cmpr6_dataa[7..0] : WIRE;
cmpr6_datab[7..0] : WIRE;
cmpr7_aeb_int : WIRE;
cmpr7_aeb : WIRE;
cmpr7_dataa[7..0] : WIRE;
cmpr7_datab[7..0] : WIRE;
cntr10 : cntr_uu7;
cntr4 : cntr_uu7;
scfifo14 : scfifo
WITH (
LPM_NUMWORDS = 3,
LPM_SHOWAHEAD = "OFF",
lpm_width = 16,
lpm_widthu = 2,
OVERFLOW_CHECKING = "ON",
UNDERFLOW_CHECKING = "ON",
USE_EAB = "OFF"
);
delayed_read_counter_after_gray_conversion[7..0] : WIRE;
delayed_write_counter_after_gray_conversion[7..0] : WIRE;
fifo_wreq_out : WIRE;
pre_rdempty : WIRE;
pre_wrfull : WIRE;
ramread_address[7..0] : WIRE;
rdusedw_delaypipe_out[7..0] : WIRE;
read_count_after_gray_conversion[7..0] : WIRE;
read_count_for_write_side[7..0] : WIRE;
read_count_to_write_side[7..0] : WIRE;
stall_pipeline : WIRE;
valid_rreq : WIRE;
valid_wrreq : WIRE;
write_count_after_gray_conversion[7..0] : WIRE;
write_count_for_read_side[7..0] : WIRE;
write_count_to_read_side[7..0] : WIRE;
wrusedw_delaypipe_out[7..0] : WIRE;
BEGIN
a_gray2bin11.gray[] = write_count_for_read_side[];
a_gray2bin3.gray[] = read_count_for_write_side[];
a_graycounter2.aclr = aclr;
a_graycounter2.clk_en = valid_wrreq;
a_graycounter2.clock = wrclk;
a_graycounter8.aclr = aclr;
a_graycounter8.clk_en = ((! stall_pipeline) & (! cmpr15_aeb));
a_graycounter8.clock = rdclk;
a_graycounter9.aclr = aclr;
a_graycounter9.clk_en = valid_rreq;
a_graycounter9.clock = rdclk;
altsyncram1.address_a[] = a_graycounter2.q[];
altsyncram1.address_b[] = ramread_address[];
altsyncram1.clock0 = wrclk;
altsyncram1.clock1 = rdclk;
altsyncram1.clocken1 = (! stall_pipeline);
altsyncram1.data_a[] = data[];
altsyncram1.wren_a = valid_wrreq;
dffe16a[].CLK = wrclk;
dffe16a[].CLRN = (! aclr);
dffe16a[].D = a_graycounter2.q[];
dffe18a[].CLK = wrclk;
dffe18a[].CLRN = (! aclr);
dffe18a[].D = read_count_after_gray_conversion[];
dffe19a[].CLK = wrclk;
dffe19a[].CLRN = (! aclr);
dffe19a[].D = add_sub5.result[];
dffe20a[].CLK = wrclk;
dffe20a[].CLRN = (! aclr);
dffe20a[].D = add_sub5.result[];
dffe21.CLK = wrclk;
dffe21.CLRN = (! aclr);
dffe21.D = wrreq;
dffe22.CLK = wrclk;
dffe22.CLRN = (! aclr);
dffe22.D = (! (((! wrreq) & (! dffe21.Q)) & cmpr7_aeb));
dffe23.CLK = wrclk;
dffe23.CLRN = (! aclr);
dffe23.D = cmpr6_ageb;
dffe25a[].CLK = rdclk;
dffe25a[].CLRN = (! aclr);
dffe25a[].D = write_count_after_gray_conversion[];
dffe26a[].CLK = rdclk;
dffe26a[].CLRN = (! aclr);
dffe26a[].D = add_sub12.result[];
dffe27a[].CLK = rdclk;
dffe27a[].CLRN = (! aclr);
dffe27a[].D = add_sub12.result[];
dffe28.CLK = rdclk;
dffe28.CLRN = (! aclr);
dffe28.D = cmpr13_ageb;
dffe29a[].CLK = rdclk;
dffe29a[].CLRN = (! aclr);
dffe29a[0].D = ((stall_pipeline & dffe29a[0].Q) # ((! stall_pipeline) & (! cmpr15_aeb)));
dffe29a[1].D = ((dffe29a[0].Q & (! stall_pipeline)) # (dffe29a[1].Q & stall_pipeline));
alt_synch_pipe17.clock = wrclk;
alt_synch_pipe17.clrn = (! aclr);
alt_synch_pipe17.d[] = read_count_to_write_side[];
alt_synch_pipe24.clock = rdclk;
alt_synch_pipe24.clrn = (! aclr);
alt_synch_pipe24.d[] = write_count_to_read_side[];
add_sub12.dataa[] = delayed_write_counter_after_gray_conversion[];
add_sub12.datab[] = cntr10.q[];
add_sub5.dataa[] = cntr4.q[];
add_sub5.datab[] = delayed_read_counter_after_gray_conversion[];
IF (cmpr13_dataa[] == cmpr13_datab[]) THEN
cmpr13_aeb_int = VCC;
cmpr13_agb_int = GND;
ELSIF (cmpr13_dataa[] > cmpr13_datab[]) THEN
cmpr13_agb_int = VCC;
cmpr13_aeb_int = GND;
ELSE
cmpr13_aeb_int = GND;
cmpr13_agb_int = GND;
END IF;
cmpr13_ageb = cmpr13_agb_int # cmpr13_aeb_int;
cmpr13_dataa[] = rdusedw_delaypipe_out[];
cmpr13_datab[] = B"11111101";
IF (cmpr15_dataa[] == cmpr15_datab[]) THEN
cmpr15_aeb_int = VCC;
ELSE
cmpr15_aeb_int = GND;
END IF;
cmpr15_aeb = cmpr15_aeb_int;
cmpr15_dataa[] = a_graycounter8.q[];
cmpr15_datab[] = write_count_for_read_side[];
IF (cmpr6_dataa[] == cmpr6_datab[]) THEN
cmpr6_aeb_int = VCC;
cmpr6_agb_int = GND;
ELSIF (cmpr6_dataa[] > cmpr6_datab[]) THEN
cmpr6_agb_int = VCC;
cmpr6_aeb_int = GND;
ELSE
cmpr6_aeb_int = GND;
cmpr6_agb_int = GND;
END IF;
cmpr6_ageb = cmpr6_agb_int # cmpr6_aeb_int;
cmpr6_dataa[] = wrusedw_delaypipe_out[];
cmpr6_datab[] = B"11111101";
IF (cmpr7_dataa[] == cmpr7_datab[]) THEN
cmpr7_aeb_int = VCC;
ELSE
cmpr7_aeb_int = GND;
END IF;
cmpr7_aeb = cmpr7_aeb_int;
cmpr7_dataa[] = wrusedw_delaypipe_out[];
cmpr7_datab[] = B"00000000";
cntr10.aclr = aclr;
cntr10.clk_en = valid_rreq;
cntr10.clock = rdclk;
cntr4.aclr = aclr;
cntr4.clk_en = valid_wrreq;
cntr4.clock = wrclk;
scfifo14.aclr = aclr;
scfifo14.clock = rdclk;
scfifo14.data[] = altsyncram1.q_b[];
scfifo14.rdreq = rdreq;
scfifo14.wrreq = fifo_wreq_out;
delayed_read_counter_after_gray_conversion[] = dffe18a[].Q;
delayed_write_counter_after_gray_conversion[] = dffe25a[].Q;
fifo_wreq_out = dffe29a[1].Q;
pre_rdempty = scfifo14.empty;
pre_wrfull = dffe23.Q;
q[] = scfifo14.q[];
ramread_address[] = a_graycounter8.q[];
rdempty = pre_rdempty;
rdfull = dffe28.Q;
rdusedw[] = dffe27a[].Q;
rdusedw_delaypipe_out[] = dffe26a[].Q;
read_count_after_gray_conversion[] = a_gray2bin3.bin[];
read_count_for_write_side[] = alt_synch_pipe17.q[];
read_count_to_write_side[] = a_graycounter9.q[];
stall_pipeline = (scfifo14.full & dffe29a[1].Q);
valid_rreq = (rdreq & (! pre_rdempty));
valid_wrreq = ((! pre_wrfull) & wrreq);
wrempty = (! dffe22.Q);
wrfull = pre_wrfull;
write_count_after_gray_conversion[] = a_gray2bin11.bin[];
write_count_for_read_side[] = alt_synch_pipe24.q[];
write_count_to_read_side[] = dffe16a[].Q;
wrusedw[] = dffe20a[].Q;
wrusedw_delaypipe_out[] = dffe19a[].Q;
END;
--VALID FILE
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