fifoasi.fit.rpt

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C4F324C8                    ;                                ;
; Device Migration List                              ; EP1C4F324C8                    ;                                ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion -- Logic Duplication          ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error       ; On                       ;
; Release clears before tri-states             ; Off                      ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/altera9.16/9.16fifoasi/fifoasi.fit.eqn.


+----------------+
; Floorplan View ;
+----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/altera9.16/9.16fifoasi/fifoasi.pin.


+-----------------------------------------------------------+
; Fitter Resource Usage Summary                             ;
+--------------------------------+--------------------------+
; Resource                       ; Usage                    ;
+--------------------------------+--------------------------+
; Logic cells                    ; 1,929 / 4,000 ( 48 % )   ;
; Registers                      ; 1,517 / 4,735 ( 32 % )   ;
; Total LABs                     ; 278 / 400 ( 69 % )       ;
; Logic elements in carry chains ; 356                      ;
; User inserted logic cells      ; 0                        ;
; Virtual pins                   ; 0                        ;
; I/O pins                       ; 157 / 249 ( 63 % )       ;
;     -- Clock pins              ; 0 / 2 ( 0 % )            ;
; Global signals                 ; 8                        ;
; M4Ks                           ; 8 / 17 ( 47 % )          ;